portmap

Name of the SPICE subcircuit or Verilog-A module to which to apply these portmap settings. Use this form (typically, together with config use=spice) when your design contains SPICE-on-leaf constructs.

Valid Values: Any valid subcircuit name or a Verilog-A module.

Here is an example on specifying a Verilog-A module using the subckt parameter.

include "basicMos.scs"
include "acf.scs"
ahdl_include "inv.va"

amsd{

   portmap subckt=inv autobus=no
    config inst=top.DUT0.I0 use=spice
    ie vsup=1.8 rhi=5 rlo=5 tr=100p

}

Note: The asterisk wildcard (*) is supported at the end of the string while specifying the subcircuit name.

Name of the Verilog module to which to apply these portmap settings. Use this specifier (typically, together with config use=hdl) when your design contains hdl components instantiated in SPICE blocks.

Valid Values: Any valid module name.

Name of the VHDL entity to which to apply these portmap settings. Use this specifier (typically, together with config use=hdl) when your design contains hdl components instantiated in SPICE blocks.

Valid Values: Any valid entity name.

Indicates whether to bind Verilog buses to SPICE ports. Valid Values:

yes

Bind Verilog buses to SPICE ports.

no

Do not bind Verilog buses to SPICE ports.

Default: yes

Specifies the reversebus name. No default.

List of bus delimiters.Valid Values: [], _, <>, none, or any single character Default: [] <>

Specifies casing for name mapping.Valid Values:

upper

Map all names to uppercase.

lower

Map all names to lowercase.

keep

Maintain name casing as it is.

Default: lower

Specifies casing for port names. Valid Values:

upper

Map all port names to uppercase.

lower

Map all port names to lowercase.

keep

Maintain port casing as it is.

Default: keep

Name of the port-bind file containing customized port bindings. 

Name of the library of precompiled cell containing custom port bindings. If the reflib parameter is provided with the portmap statement, the reffile parameter is not compiled even if it is specified with the portmap statement. The library of precompiled cell provided through the reflib parameter will be used instead of the worklib library.

The use of reflib parameter eliminates the need for special compile from AMSCB. It also limits the precompiled cell search to a specific library, thereby improving performance.

Note: The reflib parameter works only for VHDL-SPICE, and not for Verilog-SPICE.

In the example given below, the software will search for the precompiled cell sl1 in the library mylib. Notice that the reffile parameter is not specified with the portmap statement.

portmap subckt=sl1 refformat=vhdl reflib=mylib
config cell=sl1 use=spice

Name of the HDL reference file containing custom port bindings. If the reference file is not in the current working directory, include the path to its name, such as

portmap ... reffile=/user/project/myfile.v ...

The reffile parameter also supports UNIX environment variables. You can specify the file path using the UNIX environment variable $WDIR, as follows:

portmap ... reffile="$WDIR/source/analog/PLL.v"

Note: The path specified using the UNIX environment variable must be enclosed within double quotation marks.

• Use refformat to specify the format of this file. (The default format is verilog.)

• Use porttype to specify how to match the ports. (The default is by order.)

The software uses this parameter as the HDL reference when automatically generating a port-bind file containing port bindings at SPICE-to-HDL boundaries.

The reference file must satisfy the following requirements:

• The reference file must compile standalone.

• If the reference file contains any library declarations or package references, they must be available and compile successfully.

• The reference file must not contain any external language constructs.

Note: You do not need to specify the reffile parameter with the portmap card if you have specified it with the xrun command, unless you want to use a different reffile than what you specified to xrun.

Specifies how to match ports. You must also specify a reference file.

Note: The software uses this parameter when automatically generating a port-bind file. The port-bind file specifies custom bindings for the interface between SPICE and Verilog.

Valid values:

name

Match ports by name.

order

Match ports by order.

Default: order

Specifies the format of the reffile. Valid Values:

verilog

Verilog format

See also "Binding Ports using a Verilog File".

vhdl

VHDL format

Default: verilog

Name of the cell for which you want to use the stub version; you must also specify a match assignment.

Specifies which definition to use when matching the interface. The match assignment applies only when you also specify stub on the portmap statement and use=stub on the config statement.

Valid values:

verilog

Use the Verilog interface

spice

Use the SPICE interface

Default: verilog

Specifies a net as an input port. No default.

Specifies a net as an output port. No default.

Specifies a net as an input and output port. No default.

ignore

Ignores the specified ports. For example:

amsd{

ie vsup=1
portmap subckt=invx2 porttype=name ignore="vdd vss"
config cell=invx2 use=spice

}