Port Bindings between Verilog and SPICE

Port-binding considerations include case mapping and bus connections between Verilog and SPICE. The following guidelines can help you choose which method to use for your design requirements:

Design Requirements	Port-Binding Method
All buses have uniform ascending/descending port order and all ports have uniform case mapping	autobus
Customized port binding requirements	port-bind file
You have a Verilog version of a SPICE block	portmap reffile
You need to bind ports by name, rather than by order	portmap porttype

Binding Ports using autobus

To bind Verilog to SPICE ports using autobus, do the following:

Use an include statement to include the SPICE design file:
include "analog_top.sp"
Use portmap  and  config cards in the amsd block to specify the SPICE file and subcircuits that you have instantiated in Verilog modules:
amsd{
    portmap subckt=analog_top autobus=yes busdelim="<>"
    config cell=analog_top use=spice
    }

The default value for autobus on the portmap statement is yes.
Specify the AMS control file directly on the xrun command line:
xrun ... amsdcb.scs

Here is an example. The top module, testbench, instantiates one SPICE block, pll_top:

module testbench ();
reg myRESET;
reg refclk;
wire [1:0] clk_out;
.....
pll_top p1(refclk, myRESET, clk_out);
endmodule

//The SPICE subcircuit definition looks like this:

.subckt pll_top refclk reset P0_CLK[1] P0_CLK[0]
...
.ends pll_top

//You specify autobus port binding using the SPICE pll_top subcircuit in the amsd block as follows:

amsd{
    portmap subckt=pll_top autobus=yes
    config cell=pll_top use=spice
    ...
     }

//The elaborator generates the following port-bind file:

//
//portmap file for spice subckt pll_top
refclk  :       refclk  dir=inout
reset   :       reset   dir=inout
{ P0_CLK[1], P0_CLK[0] }        :       P0_CLK[1:0]     dir=inout

The SPICEname identifiers (on the left side of the colon) come from the SPICE subcircuit definition (such as .subckt pll_top refclk reset P0_CLK[1] P0_CLK[0]).

The VerilogName identifiers (on the right side of the colon) represent the port names of the Verilog module that the software generates internally. These port names can be different from the actual interface signal names in the instantiation in the top-level testbench module. In this example, for instance, the interface signal names are refclk , myRESET , and clk_out , while the port names in the port-bind file are refclk , reset , P0_CLK[1] , and P0_CLK[0].

You should change the port directions to match your design requirements ( dir=inout is the default direction setting for SPICE ports).

The software maps P0_CLK[1] and P0_CLK[0] into a bus because [] is the default bus delimiter.

Binding Ports using a Port-Bind File

Some designs require customized port binding, such as mixed-case mapping, more complicated bus forms such as those that include concatenations, and mixed ascending and descending bus orders. You can use a port-bind file to specify your customized port binding requirements.

You can use autobus to generate the initial port-bind file (.pb) automatically, then you can customize the mappings in that file. The general steps you can follow are:

Use autobus to generate the initial port-bind file (.pb).
Customize port mappings in the initial port-bind file.
Use portmap … file= to specify the port-bind file you customized.
include "analog_top.sp"
amsd{
    portmap subckt=analog_top file="analog_top.pb"
    config cell=analog_top use=spice
    }

Binding Ports using a Verilog File

If your design contains units for which you have both a Verilog and a SPICE version, you can use a Verilog file to specify your binding options. Perhaps you simulate a purely digital version of your design first, and then selectively replace some blocks with a SPICE version.

You can specify a file containing a Verilog module that defines the port mappings to use from a Verilog parent to a SPICE subcircuit instance using portmap reffile in your AMS control file. This approach lets you replace the interface of a subcircuit with that of a Verilog module.

For example:

include "analog_top.sp" amsd{ portmap subckt=analog_top reffile="analog_top.v" refformat=verilog config cell=analog_top use=spice }

In this example, analog_top.v is the Verilog file that contains the port binding information your design requires. The software applies port bindings (interfaces) defined in analog_top.v to instances of analog_top. While the elaborator uses the port bindings you define for analog_top in analog_top.v to determine how to connect instances of analog_top, the simulator simulates the analog_top subcircuit you define in analog_top.sp.

For example, analog_top.v might contain the following:

module analog_top (in1, itune, in2);
inout in1;
inout [0:1] itune;
inout in2;

analog beginend
end
module

//The analog_top subcircuit in analog_top.sp might look like this:

.subckt analog_top
+ in1 itune[0] itune[1] in2

...
.ends analog_top

//When you instantiate a subcircuit called analog_top in module top like this:

module top (ext_clk, pll_clk);
input ext_clk, pll_clk;

wire [0:1] itune;
wire res;

analog_top xana_top(
.in2(pll_clk),
.itune(itune),
.in1(ext_clk)
);

...
endmodule

Binding ports by order is not recommended when the ports in the Verilog reference file and the ports in the equivalent SPICE subcircuit do not match by order. In such situations, it is recommended that you bind ports by name using the porttype=name parameter.

Binding Ports by Name

When you need to bind the ports in your reference file by name, rather than by order, you can use the porttype specifier in a portmap statement. For example:

amsd{ ie vsup=1.8 portmap module=counter reffile="./source/digital/counter.v" porttype=name config cell=counter use=hdl }

The software uses this specifier when automatically generating a port-bind file. The default binding mechanism is by-order ( porttype=order ). However, if your design consists mostly of SPICE and Verilog ports that have the same name, but with mismatched port order, you might get a more accurate port-bind file by specifying porttype=name.

If the software cannot match ports between Verilog and SPICE successfully, the elaborator writes " not_found " as a placeholder in the port-bind file it generates (in runDir /portmap_files). You can edit this file to change all not_found keywords to the correct Verilog port names, then use the file parameter (instead of reffile and porttype) in a porttype statement to specify the file you saved, and run the simulation again.

Port Bindings between Verilog and SPICE

Binding Ports using autobus

Binding Ports using a Port-Bind File

Binding Ports using a Verilog File

Binding Ports by Name

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