This technique for importing Verilog-AMS modules into VHDL requires the use of the Cadence®library.cell:view configurations, sometimes referred to as 5x configurations, for elaboration.
Verilog-AMS is a mixed-signal language and VHDL is digital only. If you want to import a Verilog-AMS module that has explicitly declared analog ports into VHDL:
- Wrap the Verilog-AMS module so that it appears to the simulator to be a VHDL module. When you wrap a Verilog-AMS module, there are two shells: A digital Verilog shell wrapped in a VHDL shell.
- Use the
xmshellcommand to generate these shells.
If the Verilog-AMS module you want to import has wire or explicitly declared digital ports, you do not need shells because the elaborator can make the necessary connections. If you are uncertain as to whether you need shells or not, you can try elaborating without shells. If you need shells, the elaborator returns a message similar to the following:
xmelab: *E,AMSILC: Illegal port connection - :top:verilog_cell.v_a is an analog port (line: 6, file: ./foo.v) and it cannot be connected directly to a VHDL digital signal above.