Importing a Verilog-AMS Module

To import a Verilog-AMS module with explicitly declared analog ports into VHDL, do the following:

1. Use the xmvlog compiler to compile the Verilog-AMS source code for the module that you want to import.
2. Use the xmshell command to generate model import shells for the module you want to import.
3. In the source VHDL file, specify the architecture name to be used for entity.
   
   If you specified the -view option for the xmshell utility in the previous step, use that name for the architecture. If you did not specify the -view option, use verilog for the architecture name.
4. Add a clause in the source VHDL file to specify the package.
   
   If you specified the -package option for the xmshell command in step 2, use a clause such as
   use library. packagename. all;

If you did not specify the -package option, use a clause such as
   use library. HDLModels.all;
5. Compile all VHDL source code using xmvhdl.
6. Elaborate the design using the xmelab elaborator.

Example

To import the Verilog-AMS module in the file comparator_analog.v, do the following:

1. Compile the Verilog-AMS source code.
   xmvlog -ams -use5x comparator_analog.v
   If your working library is amsLib, this command compiles the module comparator into amslib.comparator:module. The -use5x option is used because 5x configurations are used later to elaborate the design.

2. Generate model import shells using xmshell. The argument to the xmshell command is the Library.Cell:View specification for the compiled module.
   xmshell -import verilog -ams -into vhdl -generic amslib.comparator:module
This command generates two shells. The digital Verilog shell, generated in the file comparator.vds, looks like this:

   module comparator(cout, inp, inm);     output cout ;     input inp ;     input inm ;       parameter td = 1.000000e09, tr = 1.000000e-09, tf = 1.000000e-09,               i = 5, j = 5 ;       comparator #(.td(td), .tr(tr), .tf(tf))               (* integer view_binding="module"; *) comparator1               (.cout(cout), .inp(inp), .inm(inm)); endmodule

   This module has an instance comparator1 of the same cell name comparator. It also has a view binding attribute module, which binds the instance to the amslib.comparator:module view. The source that is compiled into the amslib.comparator:module view is a Verilog-AMS description. This switches the elaborator into using the Verilog-AMS language.
   
   The VHDL shell, generated in a file called comparator.vhd, looks like this:

   library ieee; use ieee.std_logic_1164.all; entity comparator is     generic (          td: real := 1.000000e-09;          tr: real := 1.000000e-09;          tf: real := 1.000000e-09,          i: integer := 5,          j: integer := 5     );     port (          cout: out std_logic;          inp: in std_logic;          inm: in std_logic     ); end comparator;   architecture verilog of comparator is     attribute foreign of verilog:architecture is "VERILOG(event)     amslib.comparator:digital_shell"; begin end;

   Notice that the name of the architecture in the shell defaults to verilog.
   
   The architecture verilog has a foreign attribute amslib.comparator:digital_shell, which tells the elaborator that the architecture is actually a shell for the Verilog module compiled into the view amslib.comparator:digital_shell. This attribute causes the elaborator to switch from the VHDL language into digital Verilog.
   
   The xmshell utility also generates the following VHDL component declaration in the file comparator_comp.vhd:

   library ieee; use ieee.std_logic_1164.all;   package HDLModelsis   component comparator generic (     td: real := 1.000000e-09;     tr: real := 1.000000e-09;     tf: real := 1.000000e-09,      i: integer := 5,      j: integer := 5 );   port (     cout: out std_logic;     inp: in std_logic;     inm: in std_logic ); end component;   end HDLModels;

   In Verilog-AMS, identifiers are case sensitive. By default, mixed-case and uppercase identifiers in Verilog-AMS are escaped in VHDL shells. For example, if the Verilog-AMS module is Vlog, this identifier appears in the VHDL shell as \Vlog\. Use the -noescape option if you want the Verilog-AMS module name to be matched exactly in the shell. Do not set the CDS_ALT_NMP environment variable, which is not supported.

3. In the source VHDL file, specify that architecture verilog is to be used for entity comparator (because this example uses the default value). Add the use clause (using the default version). With these changes, the source VHDL file for this example looks like:

   -- top.vhd library ieee; use ieee.std_logic_1164.all; use work.HDLModels.all; entity top is end top;   architecture testbench of top is     signal in1, in2, output : std_logic;     for all: comparator use entity work.comparator(verilog); begin   test: process begin     in1 <= '0';     in2 <= '0';     wait; end process;   comparator12: comparator port map(output, in1, in2);   end;

   The for all statement binds the comparator instance to the design unit in amslib.comparator:verilog, which is a compiled version of the architecture verilog.

4. Compile the top-level VHDL file (top.vhd) and the VHDL package generated earlier by xmshell.

xmvhdl -v93 comparator_comp.vhd top.vhd -use5x
5. Elaborate the design with xmelab. Assuming that the corresponding 5x configuration is amslib.top:config and that the connectrules module is compiled into amslib.AMSconnect:module, you can elaborate the design with a command such as
   
   xmelab amslib.top:config AMSconnect -discipline logic

In this example, using the -discipline logic option sets the discipline of the shell ports to logic.

Related Topics

• Importing Verilog-AMS Modules into VHDL
• xmshell Command