The following section describes only those options required to import Verilog-AMS modules (that have explicitly declared analog ports) into VHDL modules. For detailed information about using the xmshell command, see "Generating a Shell with xmshell" in the "Mixed Verilog/VHDL Simulation" chapter of Cadence VHDL Simulation User Guide.
xmshell -import verilog -ams -into vhdl [ other_options ] lib . cell : view
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Indicates that the imported model is Verilog, Verilog-A, or Verilog-AMS |
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Indicates that the imported model is a Verilog-AMS (or Verilog-A) module |
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Indicates that you want to import the model into a VHDL module |
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Zero or more of the following options or the options described in "xmshell Command Options" in the "Mixed Verilog/VHDL Simulation" chapter of the Cadence VHDL Simulation User Guide. |
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Enables you to specify the package name for the VHDL package that |
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Enables you to specify the cellview name to use for the digital Verilog shell and for the architecture name of the VHDL shell. |
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If the imported Verilog-AMS module has parameters, you must use this option to make those parameters available in the shell. |
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Specifies the compiled design unit you want to import If you have not compiled the design unit, you can add the - |
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For example, if comparator is a compiled Verilog-AMS module that uses parameters, you can create a shell for it using the following command:
xmshell -import verilog -ams -into vhdl -generic comparator
If comparator is not a compiled Verilog-AMS module, you can use the -analyze option as follows to specify the source file that contains the comparator module:
xmshell -import verilog -ams -into vhdl -generic -analyze comparator.vams comparator
xmshell does not support the Verilog-AMS wreal port type.