Inherited Connections in R2L/L2R Connect Modules

You can create Real-to-Logic (R2L)/Logic-to-Real (L2R) connect modules that use inherited connections to read global power and ground values, so that you can use a dynamic supply to control the wreal/logic conversion threshold. Similarly, appropriate connect rules are created along with the new connect modules.

Here is an example of an L2R connect module that uses inherited connection:

`include "disciplines.vams"
`timescale 1ns / 1ps

connectmodule L2R_inhconn(Rout, Lin);
input Lin;
output Rout; wreal Rout;

// Inherited vdd! and vss!
wreal
(* integer inh_conn_prop_name="vdd";
integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;

wreal
(* integer inh_conn_prop_name="vss";
integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ;
parameter real vsup_min=0.5 from (0:inf); // min supply for normal operation
parameter real vlo = 0; // logic low voltage
reg supOK;
real L_conv;

initial begin
L_conv = `wrealZState;
end

always begin
if ( \vdd! - \vss! > vsup_min) supOK = 1'b1;
else supOK = 1'b0;
@(\vdd! , \vss! );
end

// Determine the value of L and convert to a real value
always begin
if ( supOK ) begin
case (Lin)
1'b0:
L_conv = \vss! ;
1'b1:
L_conv = \vdd! ;
1'bz:
L_conv = `wrealZState;
default:
L_conv = `wrealXState;
endcase // case(L_code)
end
else
L_conv = `wrealXState;
@(Lin, supOK);
end

// drive the converted value back onto the output R pin
assign Rout = L_conv;
endmodule

Here is an example R2L connect module that uses inherited connection:

`include "disciplines.vams"
`timescale 1ns / 1ps

connectmodule R2L_inhconn(Rin, Lout);
output Lout;
input Rin; wreal Rin;

// Inherited vdd! and vss!
wreal
(* integer inh_conn_prop_name="vdd";
integer inh_conn_def_value="cds_globals.\\vdd! "; *) \vdd! ;

wreal
(* integer inh_conn_prop_name="vss";
integer inh_conn_def_value="cds_globals.\\vss! "; *) \vss! ;
parameter real vsup_min=0.5 from (0:inf); // min supply for normal operation
parameter real vthi=1/1.5 from (0:1); // frac. for high thres (def=2/3)
parameter real vtlo=vthi/2 from (0:vthi); // frac. for low thres (def=1/3)
parameter real txdel=0.8n from (0:1m); // time midrange til output X
real vsup, vtl, vth, txdig=txdel/1n;
reg supOK, Xin=0, R_conv = 1'bz;

always begin
vsup = \vdd! - \vss! ;
if ( vsup > vsup_min)
begin
supOK <= 1'b1 ;
vtl <= vsup * vtlo + \vss! ;
vth <= vsup * vthi + \vss! ;
end
else begin
supOK <= 1'b0 ;
end
@(\vdd! , \vss! );
end

// Determine the value of R and convert to a logic value
always begin
if ( supOK ) begin
if(Rin >= vth)
begin R_conv = 1'b1; Xin = 0; disable GoToX; end
else if (Rin <= vtl)
begin R_conv = 1'b0; Xin = 0; disable GoToX; end
else if(Rin === `wrealZState)
begin R_conv = 1'bz; Xin = 0; disable GoToX; end
else
Xin = 1;
end
else
Xin= 1;
@(Rin, supOK, vth, vtl);
end

// see if it is a stable X
always @ (posedge(Xin)) begin: GoToX
#(txdig)
if (Xin == 1 ) R_conv = 1'bx;
end

// drive the converted value back onto the output L pin
assign Lout = R_conv;
endmodule

For L2R/R2L connect modules that use inherited connection:

The two global nets cds_globals.vdd! and cds_globals.vss! must be wreal.

It is an error if the two global nets are not wreal and need IE insertion again.

Inherited Connections in R2L/L2R Connect Modules

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