Inherited Connections in VHDL-AMS

Using the AMS Designer simulator, you can define inherited connections in a VHDL-AMS entity and architecture (only on VHDL-AMS terminals) that you instantiate in a Verilog-AMS module. With inherited connections, you can inherit and use power and ground signals that you defined at a higher level of the hierarchy in a lower level of the design using net expressions. You can use these inherited connections instead of having to create explicit power and ground terminals at each level of the design hierarchy.

You can override VHDL-AMS inherited connections netSet properties in Verilog-AMS scope only. You cannot use netSet properties in VHDL-AMS scope. Also, you cannot use supply-sensitive attributes in VHDL-AMS scope. As a result, you cannot insert a supply-sensitive connect module at the boundary between Verilog-AMS and VHDL-AMS. Inherited connections in VHDL-AMS must be scalars only. You cannot define inherited connections that are VHDL arrays or electrical vectors.

In VHDL-AMS, you define inherited connections using inh_conn_prop_name and inh_conn_def_value attributes as follows:

package cds_inhconn_attr;
   attribute inh_conn_prop_name: string;
   attribute inh_conn_def_value: string;
end cds_inhconn_attr;

Use work.cds_inhconn_attr.all;

Entity inh_conn_cell is
    <code here>
End inh_conn_cell;

Architecture demo of inh_conn_cell is
   terminal vdd: electrical;
   attribute inh_conn_prop_name of vdd : terminal is "vddProp";
   attribute inh_conn_def_value of vdd : terminal is "cds_globals.\vdd!\";
Begin
    <code here>
End demo of inh_conn_cell

The vdd terminal inherits the vddProp property which has a default value of cds_globals.\vdd!\ , where cds_globals is a Verilog module and vdd! is a global signal.

You can instantiate a VHDL-AMS entity in a Verilog-AMS module and use an explicit Verilog-AMS cds_net_set expression for an inherited connection as follows:

module top;

electrical local_net;
inh_conn_cell
    (* integer cds_net_set[0:0]={"vddProp"};
       integer vdd = "cds_globals.\ \ vdd5v! ";
    *)
inst1();

inh_conn_cell
    (* integer cds_net_set[0:0]={"vddProp"};
       integer vdd = "local_net"; // Overriding using a local net
    *)
inst2();

Endmodule