The ie statement specifies interface element parameters, optionally for a particular design unit. If you do not specify a design unit, the elaborator applies the parameter settings to all interface elements globally.
You can use an ie statement to automate the process of creating a custom discipline and connect rule for connecting the custom discipline to the electrical discipline. The software applies the custom discipline to domainless nets in your design. So, if you have digital modules with undeclared port disciplines, you can use an ie statement to specify a discrete discipline for domainless nets and the elaborator will insert the appropriate connect module automatically.
logic, you must use -amsconnrules to specify the connect rule name to use for connecting logic ports to electrical ports. You can use both mechanisms (ie statements and -amsconnrules) at the same time for designs that contain both digital modules with undeclared port disciplines and digital or Verilog-AMS modules with logic ports.The syntax for an ie statement is as follows:
ie vsup=supplyValue | connrules=inhconn_full [scope=scopeValue] [parameter=value] | currentmode
It is mandatory to specify either vsup=supplyValue or connrules=inhconn_full in the ie statement. vsup=supplyValue specifies the positive supply value in reference to vss (voltage of source and substrate, or the voltage level of the negative supply of IE). By default, vss is 0, while it can be specified as any non-zero value in the ie statement.\
The currentmode parameter enables current mode processing for connect modules. The value can be 1 or 0. By default, the value is 0.
Using ECL logic, you may need to use negative supplies values for interface elements. For example, your logic might operate between - 5V to -3.2V. In this case, for both vsup and vss , you will specify the ie statement as:
ie vsup=1.8 vss=-5
The vsup value is defined as vdd-vss. Therefore, here, vsup=(-3.2-(-5))=1.8, which is a positive value.
ie card setup, the vsup value needs to be positive because it is a relative value compared to vss to ensure that vhi>vlo.connrules=inhconn_full uses inherited connection properties for power supply and ground nets for connect modules.
For System Verilog User Defined Nettype (UDN) to Electrical connections, if you are using custom UDN and connect module, you must specify the nettype parameter in the ie card statement. The following example illustrates custom connect module insertion for a custom nettype myNT:
ie vsup=5.0 nettype="myNT"
During elaboration time, these rules are used to select the appropriate connect modules and insert them into the design.
The ie statement supports the connect rule parameters specified in the following built-in connect rules that are provided in the IUS installation hierarchy:
CR_full_fast
CR_full
CR_basic
CR_inhconn_full_fast
CR_ss_full_fast
CR_inhconn_full
CR_ss_full
CR_dynsup_full_fast
These built-in connect rules are regular connect rules with certain design style so that the all connect rule parameters are supported in ie statement transparently as ie parameters.
The AMS control block supports the ie connect rules and parameters solely based on the built-in connect rule definition. The connect rules name can be either the full name (CR_full) or the sub name (full). For example:
ie connrules=full vsup=1.8 rout=1000
ie connrules=CR_full vsup=1.8 rout=1000
You can specify zero or more scopes and zero or more parameter assignments (customizations). Any customization you specify apply to domainless nets only.
The software automatically builds the "full-fast" connect rule with the voltage supply level you specify (unless you use the connrules=connRules parameter assignment). You do not need to use -amsconnrules; you do not need to specify the connect module path or to compile any connect modules.
The software also applies any parameter=value customizations you specify, automatically, and writes information to the xrun.log file.