When disciplines are applied to nets in more than one way, the tool during elaboration determines the effective value by using the following rules of precedence.
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Discipline Specification Method |
Precedence |
|---|---|
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Explicitly defining the discipline. For example,
|
Highest precedence
Lowest precedence |
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Overriding a discipline with out-of-module references (for domainless nets). For example,
|
|
|
Defining disciplines with the
|
|
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Obtaining disciplines through the discipline resolution process (for domainless nets). |
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Define discipline with -setdiscipline option together with -ams_weak_setd (for domainless nets). |
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Determining disciplines through application of default digital discipline specifications, including use of the
used in a Verilog module and
used on the command line, specify a global default logic discipline for domainless nets that you can override using methods shown higher in the chart. |
The `default_discipline compiler directive is applied at analysis ( xmvlog ) stage to the source on which it applies. During elaboration, since the source is already analyzed, there is no way to inherit the source-level settings from the instantiating scope. The same behavior exists for other compiler directives like `default_nettype. If you want to control the discipline resolution hierarchically, use the -setdiscipline option.