SPICE Blocks in the Middle of VHDL Blocks

The AMS Designer simulator supports most VHDL block types in a design, including multi-field records, scalars, and arrays. The supported port types include VHDL pure digital entities with standard logic, ports, or port vectors; VHDL user type ports; VHDL real signal ports; VHDL-AMS entities with analog terminal; and digital ports.

A SPICE-in-the-middle arrangement within VHDL blocks consists of a hierarchy in which one or more SPICE blocks are placed between two VHDL blocks. In this arrangement, one VHDL block instantiates a SPICE block that, in turn, instantiates another VHDL block.

The reffile parameter is not required for a VHDL block that is instantiated in a SPICE block.

In the following example, a SPICE block ( dummy_spice ) is placed between two VHDL blocks ( top.vhd and leaf.vhd ):

-- top.vhd -- VHDL top
entity top is
end entity top;


architecture a_top of top is
    signal v1, v3, v5 : real;
begin
    test : entity work.dummy_spice port map (v1, v3, v5) ;
end
architecture a_top;


// subckts.m -- SPICE in the middle
.subckt dummy_spice v1 v2 v3
x1 v1 leaf p=1
x2 v2 leaf p=3
x3 v3 leaf p=5
.ends dummy_spice

-- leaf.vhd  -- VHDL leaf
entity leaf is
    generic (p : real := 2.0);
    port (signal n : out real);
end entity leaf;

architecture a_leaf of leaf is
begin
    n <= p;
end
architecture a_leaf;

SPICE Blocks in the Middle of VHDL Blocks

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