SPICE-in-the-Middle

The AMS Designer simulator supports the use of SPICE blocks in the middle of two Verilog blocks or two VHDL blocks.

A SPICE-in-the-middle arrangement consists of a hierarchy in which a Verilog-AMS block instantiates a SPICE block that, in turn, instantiates a Verilog-AMS block.

For example:

// top.v -- Verilog top
module top;
wire [0:1]a, b, out;
reg a1, b1;
ana_gate ana_gate (a, b, out) ;
endmodule

// ana_gate.sp -- SPICE in the middle
.subckt ana_gate inleft[0] inleft[1] inright[0] inright[1] out[0] out[1]
xnand1 inleft[0] inleft[1] out1 out2 out1 nand2
xnand2 inright[0] inright[1] out1 out2 out2 nand2
.ends ana_gate

// nand2.v -- Verilog leaf
module nand2( a, out );
input [0:3] a;
output out;
assign out = ~(a[0] & a[1]);
endmodule

If you are using the AMS Designer simulator with the Spectre solver and the simulation front end (SFE) parser, you can specify the Verilog-AMS module that you instantiate in the SPICE block.

To do this:

• Specify the use assignment in a config statement in an amsd block.
  For example, assuming the nand2.v reference file is in the current working directory:
  include "./ana_gate.sp"
amsd{

      portmap subckt=ana_gate autobus=yes busdelim="<>"
      config cell=ana_gate use=spice
      portmap module=nand2 reffile=nand2.v busdelim="<>"
      config cell=nand2 use=hdl
      }