Simulation Front End (SFE) Parser

The AMS Designer simulator uses the simulation front end (SFE) analog parser. With the SFE parser, the Spectre solver of the AMS Designer simulator use the same analog parser as the Spectre circuit simulator. The SFE parser provides enhanced performance and additional features, including the option to run in 64-bit mode.

The SFE parser provides:

• Native support for Spectre, SPICE, and HSPICE input files, including Spectre netlist compiled functions (NCFs)

  See "Netlist Compiled Functions (NCFs)" in the Spectre Circuit Simulator and Accelerated Parallel Simulator User Guide for more information.

• Simplified input commands with no need to run the Spectre preprocessor (see Using Simplified Input Commands with the Simulation Front End Parser for an example)
• Support for elaborating and simulating top-level instances and analyses in model files and analog control files
• Support for instances of structural Verilog-A included using an ahdl_include statement in SPICE and Spectre blocks (see also Including Structural Verilog-A in a Spectre Netlist)
• Support for hierarchical identifiers that allow you to connect to an internal node of a subcircuit
• Support for SPICE-syntax identifiers so that instance, node, and parameter names can contain characters such as # , @ , and |
• Support for several global node statements in a design
• Support for mixed Spectre and SPICE syntaxYou can include both the Spectre and SPICE languages in a design, as long as you insert the appropriate simulator language switch ( lang ). The parser checks SPICE language syntax to verify compliance with language requirements.
• Support for SPICE-syntax model binning so that you can bin models according to geometry and size
• Support for compiled C flow to boost performance, particularly when you use Verilog-A to model CMOS devices such as MOSFETs, resistors, and capacitors.The software compiles Verilog-A modules and bsource devices that you include in a Spectre or SPICE file using an ahdl_include statement during simulation.
• Support for the AMS Designer simulator in your verification flow
• Support for SPICE and Spectre user-defined functions only on analog instances inside Verilog-AMS modules (see Using SPICE and Spectre User-Defined Functions)
• Support for paramsets (for Verilog-A only)Paramsets provide a convenient way to collect parameter values so that a particular instance need only specify overrides specifically required for that instance.
• Consistent waveform formatsThe SFE parser uses the SST2 format for waveforms you request using both Tcl probes and analog control file statements. You can use the rawfmt option to output data in other formats such as wdf or fsdb.

Including Structural Verilog-A in a Spectre Netlist

Using the AMS Designer simulator with the simulation front end (SFE) parser, you can include instances of structural Verilog-A in SPICE and Spectre blocks using an ahdl_include statement. A structural module is one that instantiates another module.

The following file (res.va) contains module res and module vastruct. Because module vastruct instantiates module res, it is a structural module.

// res.va -- Verilog-A file containing a structural module, vastruct 

`include "discipline.vams"
`include "constants.vams"

module res(vp, vn);
inout vp, vn;
electrical vp, vn;
parameter real r = 0;
    analog begin
        V(vp, vn) <+ r*I(vp, vn);
        $display("Verilog-A resistor:\n");
        $display(    "Voltage=%f, Current=%f\n", V(vp, vn), I(vp, vn));
    end
endmodule

module vastruct(p, n);        // structural Verilog-A module
inout p; electrical p;
inout n; electrical n;
parameter real r=0;
    res #(.r(r)) Rva (p, n);  // instantiates module res
endmodule

You can include the file containing the structural module in a Spectre netlist file using the ahdl_include statement as follows:

global gnd
simulator lang=spectre
ahdl_include "res.va" // Includes a structural Verilog-A module

subckt sub (p n)
parameters r=500
    Rsp p int1 resistor r = r
    Rva int1 n vastruct r=r // Instantiates the structural Verilog-A module
ends

You can elaborate this design structure using the SFE parser.

Using SPICE and Spectre User-Defined Functions

Using the AMS Designer simulator with the simulation front end (SFE) parser, you can have SPICE and Spectre user-defined functions on analog instances inside Verilog-AMS modules. For example:

module foo
    ...
    vsource #(.dc(spiceUDF(5.0)) v1(in, out);
               // spiceUDF is a user-defined function inside SPICE
    ...
endmodule

You might use such a function in the calculation of instance parameter values such as ps, pd, ad, or as. For example, you might define a function f_mod as

real f_mod(real a, real b) {
    return (a-b*int((a+0.5)/b)) ;
}

and use this function in the calculation of instance parameter ad like this:

ad=f_mod*iPar("l")

Using Simplified Input Commands with the Simulation Front End Parser

Using the AMS Designer simulator with the simulation front end (SFE) parser, you do not need to run the Spectre preprocessor and the input commands are simpler.

An example of a simplified elaboration command is:

xmelab -MODELPATH subckts.m

Migrating from the Old Spectre Parser

If you were using the old Spectre parser in a previous release, you should be aware of the following differences when using the simulation front end (SFE) parser, which is turned on by default:

• The SFE parser creates instances of _cds_internal_modules_ for analog blocks.
• The SFE parser publishes global signals from cds_globals to the top scope using names that are different from those that the old parser used.
• Supply sensitivity values do not propagate to connect modules when you use the SFE parser.
• The following VHDL-AMS features are not available when you run the AMS Designer simulator with the SFE parser:
  • The -delta option to the Tcl run command
  • Break statements using break lists
  • Configuration declarations
  • The === operator