Spectre AMS Designer supports the SV bind statement that enables you to specify one or more instantiations of a module without modifying the code of the target. For example, you can use the SV bind statement at SPICE level to access the SPICE nodes and perform verification, such as adding assertion on them. For example:
//cell target
bind analog_top inc #(param_list) xinc (port map);
// instance targetbind top.i1 inc #(param_list) xinc (port map);
You can use the SV bind statement in a cell or instance specification.
In the above example, if cell analog_top or instance top.i1 is a SPICE subcircuit that is configured through the amsd control block, it triggers SV binding on SPICE.
SV binding targets the top-level SPICE instance block as well as any other instance within the scope of the hierarchy of the top-level SPICE instance block; however, there is a restriction to targeting SPICE instances below the top-level SPICE instance block. You need to ensure that the SPICE subcircuit that is instantiated within the top-level SPICE hierarchy is also instantiated in the digital instance. For example:
// Here, top.ana_top_inst of subckt ana_top is verilog-spice boundary;ana_top_level2 is an instance inside ana_top
bind top.ana_top_inst.ana_top_level2_inst inc #(param_list) xinc (port map);
//analog.scs.subckt ana_topana_top_level2_inst ana_top_level2 a b.endckt
//amscf.scs
amsd{portmap subckt=ana_topconfig cell=ana_top use=spiceportmap subckt=ana_top_level2 //This is requiredconfig cell=ana_top use=spice //This is required}
SV bind statement does not support the dot star (.*) notation.
You can ignore the SV bind statements on SPICE blocks by using the xrun option ‑ignore_svbind_spice.