Wildcard-Named Port Connections in AMS

In SystemVerilog, you can use the wildcard-named port connections, which are represented using the dot-star notation (.*), to specify port connections in the mixed-signal flow. It provides a concise and powerful implicit port connection and avoids the top-level verbosity to explicitly detail the port connection for each instance.

Currently, the following are supported:

• Ports that are basic Verilog types, Verilog-AMS signals, or a combination of both

• Ports that are of user-defined nettype (UDN). Currently, only those port connections where both the port expression and the formal port are UDNs that have structure as their user-defined type are supported.
• Supported UDN-to-UDN connections include:

• • explicit or implicit interconnects or wires coerced to UDNs

• • scalars

• • arrays

• Unsupported scenarios for all connections as explicitly named port connections

• • Usage in mixed-signal context

• • Complete list of port signals connected using a single .*.

• • Arrays and vectors

Wildcard-named port connections of UDNs with UDTs and UDRs are supported using explicit port connections.

The following do not support the .* wildcard construct:

• Complex SV data types including enum, union, class, and interface class

• Generic wreals on SV side

• SimVision

Following is an example of wildcard-named port connections:

test.sv:
`timescale 1ns/1ps
module top;
  wire m,n;
  m_ams ams(.*);
  assign m = 1;
endmodule
module m_sv(input logic m, output logic n);
endmodule

test.vams:
`include "disciplines.vams"
`timescale 1ns/1ps
module m_ams(m,n);
  input m;
  wire m;
  output n;
  electrical n;
m_sv sv(.m(m),.n(n));
analog begin
   V(n) <+ 1.8;
end
endmodule

The following example illustrates the use of arrays and vectors as port connections that are connected using wildcard-named port connection.

tb.sv:
module tb();
    reg lll;
    reg [3:0] mmm;
    dut dut_inst(.*);
endmodule

dut.v:
module dut (lll, mmm);
    input lll;
    input [3:0] mmm;
    spicex myspicex (.lll(lll),.mmm(mmm));
endmodule

spice.scs:
simulator lang=spectre
    subckt spicex lll mmm_3 mmm_2 mmm_1 mmm_0
ends spicex

spice.v:
module spicex (input lll, input [3:0] mmm);
endmodule

amscf.scs:
simulator lang=spectre
include "spice.scs"
tran tran stop=1u
amsd{

portmap subckt=spicex porttype=name reffile="spice.v"
    config cell=spicex use=spice
    ie vsup=1.8
}

xrun tb.sv dut.v spice.v amscf.scs -timescale 1ns/1ps

The following example illustrates how to connect a UDN port using wildcard-named port connection:

//Custom package

package myPkg;
typedef struct{

   real x;
}myStruct;

function automatic myStruct res_myStruct(input myStruct driver[]);

 foreach(driver[i])
      res_myStruct.x += driver[i].x;

endfunction
nettype myStruct mySum with res_myStruct;
endpackage 

//import native packages

import cds_rnm_pkg::*;

import EE_pkg::*;

//import custom packages
import myPkg::*;

//.* connected testbench
module top;
  interconnect x,y;
  interconnect u,v;

  test1 u0(.*);
  test2 u1(.*); 

endmodule // top

//Module Definitions
module test1(x,y,u,v);

  input wreal1driver x;
  input mySum y;
  inout EEnet u;
  inout wire v; 

endmodule // test 

module test2(x,y,u,v);

  output wreal1driver x;
  inout mySum y;
  inout EEnet u;
  inout wire v;

endmodule // test

Related Topic

• SystemVerilog and AMS Extensions