Values Associated with an Analog Object

You can use the function cds_get_analog_value to fetch the voltage, current, input, output, or power values associated with an analog object. This function is especially useful while writing testbenches and assertions for a design.

The cds_get_analog_value function is meant to be used only on objects belonging to a continuous domain. It can be called from within Verilog, Verilog-A, SystemVerilog (SV), or Verilog-AMS scope, and always returns a real number.

Following is the syntax of the cds_get_analog_value function.

real $cds_get_analog_value (hierarchical_name, [optional index, [optional quantity qualifier]])

Or

real $cgav (hierarchical_name, [optional index, [optional quantity qualifier]])

where,

• cgav is an alias of cds_get_analog_value. They have an identical signature.

• The object referred to by hierarchical_name must exist and must be owned by the analog solver. It must be a scalar object. hierarchical_name can be a relative or absolute path.

  You can check whether the object referred to by hierarchical_name meets these conditions by using the helper functions cds_analog_is_valid, cds_analog_exists, and cds_analog_get_width.

  The hierarchical name can refer to a Verilog-AMS context or Spectre/SPICE (a node or instance from a Spectre/SPICE format netlist) context.

• For the Spectre/SPICE netlist formats, bus or vector object notation is currently not supported. In the analog context, bus can be expanded as bits. If <> are bus delimiters, < and > cannot be used in identifier names in hierarchical path in Verilog/SystemVerilog. Verilog and SystemVerilog allow these illegal characters to be used in a name by escaping the identifier.

  In the hierarchical name, when a bus is referred to in the Spectre/SPICE context, escape the bus node bit name.

  For example, to fetch the voltage tb.DUT.n<2>, you will need to escape the node .$cgav("tb.DUT.\S<2>","potential");.

• The index can be variable, reg, or parameters so long as their value evaluates to an integral constant.

   Index applies only for vector objects.

  Example:
  $cgav("tb.DUT.n", 2, "potential").
  This statement probes voltage of the vector bit node. The return value is the voltage V(top.DUT.n[2]).

  Note that the $cgav index feature works only if the top.n[2] vector is in the Verilog-AMS context or scope.
• The quantity qualifier can be potential , flow , pwr , or param. If none is specified, potential is assumed.

If any of the above conditions is not satisfied, the behavior of the cds_get_analog_value function will be undefined. To test that these conditions are satisfied by the analog object being referenced and to create more reusable testbench code with failsafe behavior, you can use the following helper functions:

• cds_analog_exists - Function to determine if the object is a member of the analog domain.
  
  Signature:
  
  int $cds_analog_exists(hierarchical_name, [optional index])

Return value:
  
  1/0

(where 1 is true and 0 is false)
  
  Arguments:
  • hierarchical_name can be in pure Verilog syntax.

• • If index is not specified, the object is assumed to be scalar.
• cds_analog_get_width - Function to determine the width of an object
  
  Signature:

int $cds_analog_get_width(hierarchical_name)

Return value:
  
  width of the object
• cds_analog_is_valid - Function to test if the reference object can be probed using the cds_get_analog_value function.
  
  Signature:

int $cds_analog_is_valid(hierarchical_name, [optional index, [optional quantity qualifier]])

Return value:
  
  1/0

Arguments:
  • hierarchical_name can be in pure Verilog syntax.

• • If index is not specified, the object is assumed to be scalar.

• • If quantity qualifier is not specified, it is assumed that the hierarchical name is a net.
• cds_set_temperature - Function to change the global circuit temperature parameter during simulation.
  
  Signature: 
  
  $cds_set_temperature(expression)
  
  Return value:
  
1/0 

  Argument:
  
  expression should be a real-type expression that represents the temperature to be set in degree Celsius. You can use variables and parameters in the expression.
• simprobe - Function to allow probing of values within a sibling instance during simulation in analog context.
  
  Signature:
  
  $simprobe( <inst_name> (string), <param_name> (string), [ optional real valued expression ] )
  
  Return value:
  
  Double value of the parameter that is probed. 
  
  Arguments:
  
  • inst_name the name of the sibling instance in the current parent instance.
  • param_name is the output variable to be probed in inst_name.
  • If a parameter is not found and the optional real valued expression is set, then that would be the output.
• $simprobe$str -  Function to allow probing of values within a sibling instance during simulation in analog context.
  
  Signature:
  
  $simprobe$str( <inst_name> (string), <param_name> (string), [ optional string expression] )
  
  Return value:
  
  String value of the parameter that is probed. 
  
  Arguments:
  
  • inst_name the name of the sibling instance in the current parent instance.
  • param_name is the output variable to be probed in inst_name.
  • If a parameter is not found and the optional real valued string is set, then that would be the output.