Strength-Based Interface Element (SIE)

Strength-based Interface Element (SIE) is a new simulation technology that accurately models and simulates the analog or digital interface in a mixed-signal design. In SIE, both strength and logic levels of a digital signal are converted with the impedance and voltage level of the Thevenin equivalent circuit representing the analog interface. As a result, the signal value and direction on the mixed-signal net are resolved automatically and dynamically.

SIE's simulation accuracy (including the timing and logic value on mixed-signal nets of the currently supported features) is fully backward-compatible with virtually the same simulation performance. SIE:

• supports all strength-based Verilog models on the analog or digital interface. For example:
  • tran gate - tran , tranif1 , rtranif0

• • wire - supply1 , supply0

• • buffer
    assign (pull1, weak0) y = x;
buffif (pull1, strong0) B1 (y, x, c);
• maintains natural connection of all devices on the Verilog side of the connect module, instead of segregating drivers from receivers.
• eliminates the analog loading effect on Verilog supply1 or supply0 net.
• provides an easy design configuration-and-verification flow with various strength-based Verilog models.

The SIE mode is turned on by default. However, if you have a design that contains connect modules that do not support SIE, the simulation automatically runs in non-SIE mode and a warning message is displayed. The log file also indicates that the simulation is running in non-SIE mode. For designs that do not use ie statement or connect modules/connect rules, the log file does not display any information related to SIE.

To run the simulation in SIE mode, all connect modules inserted in the design must support SIE, otherwise, the simulator automatically enables the non-SIE mode. It is recommended that you configure your design with the basic, full, or full_fast connect rules (available in the installation) by using one of the following methods, as applicable to your flow:

• In ADE, click Setup > Connect Rules
• In the xrun command-line flow, use the ie statement in the amsd block. For example, ie connrules=< conn_rule_name >.
• In the xmelab or xrun command-line flow, specify the connect rules. For example, ConnRules_18V_full_fast.

The following new set of parameters and their default values for driver output resistance corresponding to the Verilog signal strength resistances are defined in the full_fast connect rules:

The connect modules that support SIE contain the $SIE_input system task that enables you to obtain the input value and strength of the digital drivers. The $SIE_input system task takes two arguments. The first argument can be any digital scalar net. The second argument depends on the nettype of the first argument.

• If the first argument is a scalar logic wire, the second argument should be wire [7:0]
• If the first argument is scalar wreal, the second argument should also be scalar wreal
• If the first argument is a scalar SV wreal, the second argument should also be a scalar SV wreal with the same nettype

For example:

$SIE_input(Din, Dval);

SIE is supported in all existing connect modules of basic, full, and full_fast connect rules available in the AMSD installation. SIE is also supported in the AMS-CPF and IEEE 1801 standard (UPF) flows.

To model the bidirectional behavior of WTRAN models with SV-wreal nettypes, you can use the $cds_get_external_drivers system task.

Related Topics

• ie
• Writing Bidirectional Model Behavior
• xrun Command-Line Options for Mixed-Signal Designs