Verilog 2001 Configuration File

The amsd block supports Verilog 2001 configuration (specified using the -libmap and -compcnfg xrun options). If the configuration information is specified in the amsd block as well as the Verilog 2001 configuration file, then the following rules apply:

Configuration information specified in the amsd block takes higher priority than Verilog 2001 configuration.

For instances that are not specified as use=spice in the amsd block, Verilog 2001 configuration is considered.

For Verilog 2001 configuration, the top-level design unit is specified using the design parameter in the configuration file.

Consider an example where you have the following:

//file top.v

module top();

clock a1(...); //
clock a2(...);
clock a3(...);

endmodule

//file clock.v ->

module clock(...);

//rtl description endmodule

//clock.vg -> gateLib

clock(...);

//gate-level description endmodule

The Verilog 2001 configuration file config01.v is specified as follows:

config cfg1;

design rtlLib.top

default liblist rtlLib;

instance top.a3 liblist gateLib:

endconfig

In a pure digital run, the binding result would be as follows:

a1; a2=>rt1Lib; a3=>gateLib

If you want to configure instance a1 as spice view, you can use the config statement in the amsd block as follows:

include "clock.scs"

amsd{

portmap subckt=clock
config inst= top.a1 use=spice

}

When the simulation is run, the binding result would be as follows:

a1=>spice ; a2=>rt1Lib ; a3=>gateLib

For more information on how to configure the contents of a design, refer to Section 13 of the Verilog 2005 LRM.

Verilog 2001 Configuration File

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