config

The config statement specifies which definition you want to use for particular cells or instances.

config use=definition [parameter=value]

The config statement must always be placed after the portmap statement in an amsd block.

Valid parameter=value assignments for the config statement are as follows:

`cell`	One or more names of cell references in the NC HDLs for which you want to use the specified definition (`use=definition`). If you specify more than one cell name, you must use double quotation marks around the list: `config cell="subA subB subC" use=spice` `config cell=dsp use=hdl` Note: The asterisk wildcard (`*`) is supported at the end of the string while specifying the cell name.
`inst`	Full hierarchical path to one or more names of instance references in the NC HDLs for which you want to use the specified definition. If you specify more than one instance, you must use double quotation marks around the list. `config inst="top.inst1 top.inst2 top.inst3" use=spice` In addition, if the hierarchical path of an instance contains an index (vector bit), you must use double quotation marks around the instance definition. `config inst="top.inv_chain.forgentblk[0].case_blk0.inv" use=spice` You can use the `inst` assignment to specify iterated instances, use wildcards and escaped identifiers as shown in the examples below. Moreover, it is also possible bind multiple iterated instances from different hierarchies. For example: `amsd{` `portmap module=buf1 porttype=name autobus=yes` `config inst="tb.wrapper.dut.I0<0>.B<>" use=hdl` `portmap module=buf1 porttype=name autobus=yes` `config inst="tb.wrapper.dut.I1<>.B<0>" use=hdl` `portmap module=buf1 porttype=name autobus=yes` `config inst="tb.wrapper.dut.I2<>.B<>" use=hdl` `}` You can specify multiple iterated instances with a single `inst` assignment as follows: `portmap module=buf1 porttype=name autobus=yes reffile="buf.v"` `config inst="tb.wrapper.dut.I0<1>.B0<0> tb.wrapper.dut.I0<1>.B0<1> tb.wrapper.dut.I0<1>.B0<2>" use=hdl.`
`use`	Specifies which definition you want the simulator to use. Valid values:
	`hdl`	Use the HDL definition
	`spice`	Use the SPICE definition
	`stub`	Replace the specified cell with a stub version (which has the same interface but no content); you must specify a `cell` parameter assignment; you can specify a `match` choice of `verilog` or `spice` in the `portmap` statement for the stub
	No default. You must specify a `use` assignment.
`exclude`	Specifies a scope that will be excluded from the application of the `use` parameter setting in the `config` card. In the example below, the `use=hdl` setting will be applied to all instances of cell `inv` except those within the scope `mid2_block` , which is a block within `mid_block.` `amsd{` `...` `config cell=mid_block use=spice` `config cell=inv use=hdl exclude=mid2_block` `}`

You must specify either a cell or an instance or both. If you specify both, the instance must be an instance of the cell.

Here are some examples:

amsd{
    config cell="subA subB subC" use=spice
    config inst=top.I1.I2 use=spice
    config cell=dac use=hdl
    }

include "analog_top.cir"
amsd{
    portmap stub=analog_top match=spice  // SPICE stub
    config inst=top.xana_top2 use=stub

    portmap subckt=analog_top autobus=yes  // SPICE subcircuit
    config inst=top.xana_top3 use=spice

    portmap subckt module=nand2 file=nand2.pb  // SPICE-in-the-middle
    config inst=top.a1.x1 use=hdl

    portmap stub="worklib.analog_top:module" match=verilog  // Verilog stub
    config inst=top.xana_top4 use=stub
    }

config

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