As part of the application-centric enhancements in the Xcelium mixed-signal verification, a set of related SystemVerilog and SPICE co-simulation use cases can be now enabled using a single xrun/xmelab command-line option, -dms_cosim.
If you are running co-simulations for your design or verification, you can use the -dms_cosim option to automatically enable the following technologies for a more optimized and out-of-box experience with mixed-signal designs:
- Automatically process Out-Of-Module References to SPICE (
-autospiceoomr) - Optimize analog connectivity across digital/SV blocks using discipline resolution optimization (
-amsdropt) while shutting off the more comprehensive discipline resolution algorithm from Verilog-AMS standard (-disres none) - Enable advanced SystemVerilog and mixed-signal connectivity improvements such as connecting SystemVerilog Hierarchical UDT to electrical, SystemVerilog interface to DMS/Verilog-AMS signals, SystemVerilog multi-dimensional array to SPICE/electrical ports, coercion for SystemVerilog interfaces/program/checker blocks, using wildcard-named port connections in SV bind statements (all using one option
-sv_ms).
The following is an example of a design where discipline resolution is enabled (-disres none is disabled) because the design has mixed signal content that requires more comprehensive mixed-signal elaboration.
command: top.sv -64 amscf.scs -timescale 1ns/100ps -dms_cosim child.vams============top.sv=============module top;wire [0:2]foo ;spice_driver spice_drvr0 (foo); //SPICE DRVRdig_receiver dig_rcvr0(foo);endmodulemodule dig_receiver(input wire [0:2]in);spice_dut rcvr0 (in);//SPICE DUTendmodulemodule spice_driver (output wire [0:2] out);//DIGITAL VERSION OF spice_driverendmodulemodule spice_dut(input wire [0:2] in);//DIGITAL VERSION of spice_dutendmodule
============child.vams==========`include "disciplines.vams"module child();electrical a;endmodule
============amscf.scs===========include "./ana_gate.sp"amsd {portmap subckt=spice_driver autobus=yes file="./spice_driver.pb"config cell=spice_driver use=spiceportmap subckt=spice_dut autobus=yes file="./spice_dut.pb"config cell=spice_dut use=spiceie vsup = 5.0}============ana_gate.sp==========simulator lang=spice.subckt spice_dut in_0 in_1 in_2.ends.subckt spice_driver out[0] out[1] out[2].ends
=============================
All such designs consisting of .vams, .vhams, or .svams, are considered as a co-simulation application and the following DISCOS warning is displayed:
xmelab: *W,DISCOS: [DMSINFO] '-disres none' which is one of the automated -dms_cosim optimizations is disabled for this design because the design has mixed signal content which requires more comprehensive mixed-signal elaboration.
The following is an example of how using the -dms_cosim option optimizes mixed-signal elaboration algorithms for AMS co-simulation applications (SV+SPICE). Auto-detected co-sim design, switching elaboration to co-simulation(-disres none and -amsdropt) mode.
command: xrun top.sv -64 amscf.scs -timescale 1ns/100ps -dms_cosim================top.sv================module top;wire [0:1][0:2]foo ;spice_driver spice_drvr0 (foo[0]); //SPICE DRVRspice_driver spice_drvr1 (foo[1]); //SPICE DRVRdig_receiver dig_rcvr0(foo);endmodulemodule dig_receiver(input wire [0:1][0:2]in);spice_dut rcvr0 (in[0]);//SPICE DUTspice_dut rcvr1 (in[1]);//SPICE DUTendmodulemodule spice_driver (output wire [0:2] out);//DIGITAL VERSION OF spice_driverendmodulemodule spice_dut(input wire [0:2] in);//DIGITAL VERSION of spice_dutendmodule================amscf.scs==============include "./ana_gate.sp"amsd {portmap subckt=spice_driver autobus=yes file="./spice_driver.pb"config cell=spice_driver use=spiceportmap subckt=spice_dut autobus=yes file="./spice_dut.pb"config cell=spice_dut use=spiceie vsup = 5.0}============ana_gate.sp=================simulator lang=spice.subckt spice_dut in_0 in_1 in_2.ends.subckt spice_driver out[0] out[1] out[2].ends==============================
