SPICE

.subckt pll_top refclk reset p0_clk_0 p0_clk_1
...

There are five ways to specify the port mapping for the SPICE instance p1 in Verilog module top :

• Using the reference file name with the xrun command:
  xrun work.scs top.v 

//work.scs
amsd{
...
portmap
subckt=top
config cell=top use=spice
}
  With this specification, the port association between Verilog and SPICE will be established using the information from the Verilog reference file top.v specified in the xrun command. The port pll_clk in the resulting port bind file will be mapped as:
  { p0_clk_0, p0_clk_1 }  :      P0_CLK[1:0]
• Using simple portmap card:
  amsd{
...
portmap subckt=pll_top
...
}
  With this specification, the port association between Verilog and SPICE will be established using the information in the SPICE subcircuit. The port pll_clk in the resulting port bind file will be mapped as:
  { p0_clk_0, p0_clk_1 }  :        P0_CLK[0:1]
• Using reffile in portmap card with default of porttype=order
amsd{
...
portmap subckt=pll_top reffile="top.v"
...
}
With this specification, the port association between Verilog and SPICE will be established using the information from both the reference Verilog module and the reference SPICE subcircuit. In other words, their port order will be preserved from their original source files. The port pll_clk in the resulting port bind file will be mapped as:
  { p0_clk_0, p0_clk_1 }  :      P0_CLK[1:0]
• Using reffile in portmap card with porttype=name
amsd{
...
portmap subckt=pll_top reffile="top.v" porttype=name
...
}
With this specification, the port association between Verilog and SPICE will be established using the information in the reference Verilog module, both for the name and its port order. The port pll_clk in the resulting port bind file will be mapped as:
  { p0_clk_1, p0_clk_0 }  :        P0_CLK[1:0]
• Using file in portmap card
  amsd{
...
portmap subckt=pll_top file="pll_top.pb"
...
}
With this specification, the port association between Verilog and SPICE will be established using the information in the given port bind file, pll_top.pb. You can specify the port binding information in the pll_top.pb file for port pll_clk  to reflect the exact connection expected at the Verilog/SPICE boundary. For example:
  { p0_clk_1, p0_clk_0 }  :        P0_CLK[1:0]

Related Topics

• portmap
• Spice-to-Verilog Port Mapping
• Implicit and Explicit Port Mapping