Product Documentation
Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Product Version 22.09, September 2022

deposit

Sets the value of an object. Behaviors that are sensitive to value changes on the object run when the simulation resumes, just as if the value change was caused by the Verilog or VHDL code.

In this release, you cannot set the value of an analog object. In addition, you cannot use the deposit command to set the value of digital objects while the analog solver is active.

The deposit command without a delay is similar to a force in that the specified value takes effect and propagates immediately. However, it differs from a force in that future transaction on the signal are not blocked.

You can specify that the deposit is to take effect at a time in the future (-after -absolute) or after some amount of time has passed (-after -relative). In VHDL, a deposit with a delay is different from Verilog in that it creates a transaction on a driver, much the same as a VHDL signal assignment statement. Use the -inertial or -transport option to deposit the value after an inertial delay or after a transport delay, respectively.

For VHDL, you can deposit to ports, signals, and variables if no delay is specified. If a delay is specified, you cannot deposit to variables or to signals with multiple sources.

For Verilog, you can deposit to ports, signals (wires and registers), and variables.

If the object is a memory or a range of memory elements, the specified value is deposited into each element of the memory or into each element in the specified range.

If the object is currently forced, the specified value appears on the object after the force is released, unless the release value is overwritten by another assignment in the meantime.

If the object is a register that is currently forced or assigned, the deposit command has no effect.

The value assigned to the object must be a literal. The literal can be generated with Tcl value substitution or command substitution. (See the "Verilog Value Substitution" and "Command Substitution" sections, in the "Basics of Tcl" appendix of Cadence Verilog Simulation User Guide for details on Tcl substitution.)

For VHDL, the value specified with the deposit command must match the type and subtype constraints of the VHDL object. Integers, reals, physical types, enumeration types, and strings (including std_logic_vector and bit_vector) are supported. Records and non-character array values are not supported, but objects of these types can be assigned to by issuing commands for each subelement individually.

The object to which the value is to be deposited must have read/write access. An error is generated if the object does not have this access. See Access to Digital Simulation Objects.

For an SV-UDN net, you can deposit value to a scalar net, whole array, or bit-select and part-select of arrays. And, you can use order-based or name-based approach to deposit a value. For the name-based approach, the filed order can be different from that defined in the SV-UDN net. You can also assign real'z or real'x values to SV-UDN.

Additionally, you can use the xm_deposit system task to assign value on an SV-UDN net. The syntax is: xm_desposit (“<name”, “value”). The value string should not contain any space; and, for the scalar UDN or bit-selected UDN array, the value string should not contain {}. For example:

$xm_deposit("dut.ve[1:2]", "{V:1.7,R:10,I:real'z}{1.7,real'x,20}");

The deposit command is supported on user-defined nettypes (UDNs).

deposit Command Syntax

deposit object_name [=] value
    [-after time_spec {-relative | -absolute}]
    [-inertial]
    [-transport]
    [-generic]

deposit Command Options

This section describes the options that you can use with the Tcl deposit command.

-after <time_spec> [<value> ‑after <time_spec>...]

Causes the assignment to occur at a time in the future rather than immediately. The time specified using the time_spec argument can be relative or absolute. Relative is the default.

If you do not specify a time, the assignment happens immediately before simulation resumes. If the specified time is the current simulation time, the assignment occurs after simulation resumes but before time advances.

-relative Causes the assignment to occur after the amount of time specified in time_spec has passed. This is the default.
-absolute Causes the assignment to occur at the simulation time specified in time_spec.
-inertial Deposits the value after an inertial delay.
-transport Deposits the value after a transport delay.
-generic Deposits generic value. This operation might lead to violation of globally static bounds.

deposit Command Example

Digital Verilog-AMS examples:

The following command assigns the value 8'h1F to r[0:7]. No time for this assignment is specified, so the assignment occurs immediately. The equal sign is optional.

xcelium> deposit r[0:7] = 8'h1F

The following command assigns 25 to r[8:15] after simulation resumes and 1 time unit has elapsed.

xcelium> deposit r[8:15] = 25 -after 1

The following command assigns 25 to r[8:15] at simulation time 1 ns.

xcelium> deposit r[8:15] = 25 -after 1 ns -absolute

The following command sets the value of x to the current value of w. The assignment occurs at simulation time 10 ns.

xcelium> deposit x = #w -after 10 ns -absolute

The following command uses both command and value substitution. The object y is set to the value returned by the Tcl expr command, which evaluates the expression #r[0] & ~#r[1] using the current value of r.

xcelium> deposit y = [expr #r[0] & ~#r[1]]

The following command shows the error message that is displayed if you run in regression mode and then try to deposit a value to an object that does not have read/write access.

xcelium> deposit clrb 1
xmsim: *E,RWACRQ: Object does not have read/write access:
                 hardrive.h1.clrb.

VHDL examples:

The following command deposits the value 1 to object:t_nickel_out (std_logic). The equal sign is optional.

xcelium> deposit :t_nickel_out = '1'

The following command deposits the value 1 to object:top:DISPENSE_tempsig (std_logic).

xcelium> deposit :top:DISPENSE_tempsig '1'

The following command deposits the value 0 to object:t_dimes (std_logic_vector) after 10 ns has elapsed.

xcelium> deposit -after 10 ns -relative :t_DIMES {"00000000"}

The following command deposits the value TRUE to object stoppit (boolean).

xcelium> deposit stoppit true

The following command deposits the value 10 to object:count (integer).

xcelium> deposit :count 10

SV-UDN examples:

The following example illustrates the SV-UDN structure and how to apply the deposit command to a scalar net with name-based value:

typedef struct {
    real V;
    real I;
    real R;
}  EEstruct;

Time: 0 FS: tb.ve = ('{V:0, I:0, R:1e+06},'{V:0, I:0, R:1e+06},'{V:0, I:0, R:1e+06})
Time: 0 FS: tb.e = '{V:0, I:0, R:1e+06}

xcelium> deposit tb.e {V:1.2, I:real'z, R:500};
Time: 40 NS: tb.e = '{V:1.2, I:`wrealZState, R:500}

The following example illustrates how the deposit command applies value on bit-select of an array with order-based value. Values 1.2, real’z, and 50 are applied on real variable V, I, and R, respectively in the order in which it is defined/declared in the structure:

# Bit-Selected : Order-Based Value
xcelium> deposit tb.ve[1] {1.2, real'z, 50}

Time: 40 NS: tb.ve = ('{V:0, I:0, R:1e+06},'{V:1.2, I:`wrealZState, R:50},'{V:0, I:0, R:1e+06})

The following example applies the deposit command on part-select of an array with order-based value:

xcelium> deposit tb.ve[2:1] {{V:1.0, R:10, I:real'z} {1.5, real'x, 20}}

Time: 60 NS: tb.ve = ('{V:1, I:`wrealZState, R:10},'{V:1.2, I:`wrealZState, R:50},'{V:0, I:0, R:1e+06})
Time: 60 NS: tb.ve = ('{V:1, I:`wrealZState, R:10},'{V:1.5, I:`wrealXState, R:20},'{V:0, I:0, R:1e+06})

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