force

 The Tcl force command sets a specified object to a given value and forces it to retain that value until another force is placed on it or until it is released with:

• A release command
• A force -release command
• A deposit -release command

The new value takes effect immediately, and, in the case of Verilog wires and VHDL signals and ports, the new value propagates throughout the hierarchy before the command returns. Releasing a force causes the value to immediately return to the value that would have been there if the force had not been blocking transactions.

The object cannot be:

• A Verilog memory

• A Verilog memory element

• A bit-select or part-select of a Verilog register

• A bit-select or part-select of an unexpanded Verilog wire

• A VHDL variable

For Verilog, a force created by the force command is identical in behavior to a force created by a Verilog force procedural statement. The force can be released by a Verilog release statement or replaced by a Verilog force statement during subsequent simulation.

The value must be a literal, and the literal is treated as a constant. Even if the literal is generated using value substitution or Tcl's expr command, the value is considered to be a constant. The forced value does not change if objects used to generate the literal change value during subsequent simulation.

For VHDL, the value specified with the force command must match the type and subtype constraints of the VHDL object. Integers, reals, physical types, enumeration types, and strings (including std_logic_vector and bit_vector) are supported. Records and non-character array values are not supported, but objects of these types can be assigned to by issuing commands for each subelement individually.

Forces created by the force command and those created by a Verilog force procedural statements are saved if the simulation is saved.

The force command can also be used on wreals with the following limitations:

• The value being forced should be a literal value. The Tcl value substitution (value x) and expr command (expr 2+3) are supported.

• Out of module references (OOMRs) to wreals that require support of Hierarchical IE optimization and IE insertion in VHDL scope are not supported.

You can apply the force command on bit-select and part-select of wreal arrays, or on an entire wreal array. In case of part-select, the number of forced values should be equal to the width of part-select. In case of entire wreal arrays, the number of forced values should be equal to the width of the array.

The following net types are supported:

• wreal array, explicitly defined in Verilog-AMS
  module foo();
  wreal ra[3:0];
endmodule

• wire vector defined in Verilog-AMS or SystemVerilog file, and coerced to wreal array
  module top();
  wire [3:0]ra;
  foo inst(ra);
endmodule

module foo();
  wreal ra[3:0];
endmodule

• interconnect vector defined in a SystemVerilog file, and coerced to wreal array
  module top();
  interconnect [3:0]ra; <<< applying TCL force/release on each bit will be supported
  foo inst(ra);
endmodule

module foo();
  wreal ra[3:0];
endmodule

A wreal net can also be forced to `wrealXState and `wrealZState.

For an SV-UDN net, the forced value overrides all previous forces on the entire SV-UDN structure. The forced value is frozen, and the resolution function result is overridden always, until another force or release command is applied. The forced value is the final value of net, and no resolution function is executed at that time.

You can apply the force command on scalar, whole array, bit-select, or part-select of arrays of SV-UDN. And, you can use order-based or name-based approach to force a value. For the name-based approach, the filed order can be different from that defined in the SV-UDN net. You can also assign real'z or real'x values to SV-UDN.

A limitation of applying the force command on an SV-UDN net is that you cannot force value on individual/specific fields of the SV-UDT. You must specify all the fields of the SV-UDN structure in the force command.

Additionally, you can use the xm_force system task to assign value on an SV-UDN net. The syntax is: xm_force (“<name”, “value”). The “value” string should not contain any space; and, for the scalar UDN or bit-selected UDN array, the “value” string should not contain {}. For example:

$xm_force("dut.ve[0:1]", "{V:1.0,R:10,I:real'z}{1.5,real'x,20}");

force Command Syntax

force <object-name> [=] <value>


force Command Options

None.

force Command Examples

The following examples illustrate use cases for the force command:

• Digital Verilog-AMS
• VHDL
• Wreal
• SV-UDN

Digital Verilog-AMS Examples

The following command forces object r to the value `bx. The equal sign is optional.

xcelium> force r = `bx

The following command uses value substitution. Object x is forced to the current value of w.

xcelium> force x = #w

The following command uses command substitution and value substitution. Object y is forced to the result of the Tcl expr command, which evaluates the expression #r[0] & ~#r[1] using the current value of r.

xcelium> force y [expr #r[0] & ~#r[1]]

The following command shows the error message that is displayed if you run in regression mode and then use the force command on an object that does not have write access.

xcelium> force clrb 1
xmsim: *E,RWACRQ: Object does not have read/write access:
                                       hardrive.h1.clrb.

VHDL Examples

The following command forces object :t_nickel_out (std_logic) to 1. The equal sign is optional.

xcelium> force :t_nickel_out = '1'

The following command forces object :top:DISPENSE_tempsig (std_logic) to 1.

xcelium> force :top:DISPENSE_tempsig '1'

The following command forces object :t_dimes (std_logic_vector) to 0.

xcelium> force :t_DIMES {"00000000"}

The following command forces object is_ok (boolean) to TRUE.

xcelium> force :is_ok true

The following command forces object :count (integer) to 10.

xcelium> force :count 10

Wreal Examples

The following command applies the force command on bit-select of wreal arrays:

Time: 100 NS: top.wrvInst.ra = (0,0,0,0)
xcelium> force top.wv[3] 1.2
Time: 100 NS: top.wrvInst.ra = (1.2,0,0,0)

The following command applies the force command on part-select of wreal arrays:

Time: 100 NS: top.wrvInst.ra = (0,0,0,0)
xcelium> force top.wrvInst.ra[2:1] {1.5 1.8}
Time: 200 NS: top.wrvInst.ra = (0,1.5,0,0)
Time: 200 NS: top.wrvInst.ra = (0,1.5,1.8,0)

The following command applies the force command on an entire wreal array:

Time: 100 NS: top.wrvInst.ra = (0,0,0,0)
xcelium> force top.wrvInst.ra {1.8 1.6 1.4 1.2}
Time: 100 FS: top.wrvInst.ra = (1.8,0,0,0)
Time: 100 FS: top.wrvInst.ra = (1.8,1.6,0,0)
Time: 100 FS: top.wrvInst.ra = (1.8,1.6,1.4,0)
Time: 100 FS: top.wrvInst.ra = (1.8,1.6,1.4,1.2)

The following command forces the wreal net top.wrvInst.r to a value real'x.

xcelium> force top.wrvInst.r=real'x

The following command forces the wreal net top.wrvInst.r to a value real'z.

xcelium> force top.wrvInst.r=real'z

The following command forces wreal net top.wrvInst.ra to ` wrealXState and `wrealZState.

xcelium> force top.wrvInst.ra {real'x 1.6 1.4 real'z}
Time: 100 NS: top.wrvInst.ra = (`wrealXState,0,0,0)
Time: 100 NS: top.wrvInst.ra = (`wrealXState,1.6,0,0)
Time: 100 NS: top.wrvInst.ra = (`wrealXState,1.6,1.4,0)
Time: 100 NS: top.wrvInst.ra = (`wrealXState,1.6,1.4,`wrealZState)

SV-UDN Examples

The following example illustrates the SV-UDN structure and how the force command applies a name-based value to a scalar net. Values 1.2, real’z, and 500 are forced on real variable V, I, and R, respectively.

typedef struct {
real V;
real I;
real R;
} EEstruct;

Time: 0 FS: tb.ve = ('{V:0, I:0, R:1e+06},'{V:0, I:0, R:1e+06},'{V:0, I:0, R:1e+06})
Time: 0 FS: tb.e = '{V:0, I:0, R:1e+06}

xcelium> force tb.e {V:1.2, I:real'z, R:500};
Time: 40 NS: tb.e = '{V:1.2, I:`wrealZState, R:500}

The following example illustrates how the force command applies value on bit-select of an array with order-based value. Values 1.2, real’z, and 50 are forced on real variable V, I, and R, respectively in the order in which it is declared in the structure:

xcelium> force tb.ve[1] {1.2, real'z, 50}

Time: 40 NS: tb.ve = ('{V:0, I:0, R:1e+06},'{V:1.2, I:`wrealZState, R:50},'{V:0, I:0, R:1e+06})

The following example applies the force command on part-select of an array:

# Part-Selected
xcelium> force tb.ve[2:1] {{V:1.0, R:10, I:real'z} {1.5, real'x, 20}} //named-based and order-based approach

Time: 60 NS: tb.ve = ('{V:1, I:`wrealZState, R:10},'{V:1.2, I:`wrealZState, R:50},'{V:0, I:0, R:1e+06})

Time: 60 NS: tb.ve = ('{V:1, I:`wrealZState, R:10},'{V:1.5, I:`wrealXState, R:20},'{V:0, I:0, R:1e+06})

Related Topics

• Enabling Read, Write, or Connectivity Access to Digital Simulation Objects

• Forcing and Releasing Signal Values

• Basics of Tcl appendix in Cadence Verilog Simulation User Guide