Spice-to-Verilog Port Mapping

In the AMS Designer simulator, if you have a SPICE instance in a Verilog module, you can specify the port mappings for the SPICE instance in any of the following ways:

Using the reference file name with the xrun command

Using a simple portmap card

Using reffile in a portmap card with default of porttype=order

Using reffile in a portmap card with default of porttype=name

Using a file in a portmap card

In addition to the port mapping information between SPICE and Verilog representations of the given block, the automatically generated port bind file provides some more information in the form of comments. This information includes information like the SPICE subcircuit name and the Verilog module name for which the port bind file is generated.

Following is an example of a port bind file with some typical comments.

//*** dummy_spice.pb ***

//* This file is automatically generated.

//* (c) Copyright 2007-2008 Cadence Design Systems, Inc.

//* All rights reserved.

//*

//* Portbind file for:

//* SPICE subckt dummy_spice : HDL module dummy_spice

//* SPICE port :      HDL port :      HDL Parameters



{ a_0, a_1, a_2 }      :      a[0:2]  :      dir=output vh_type=STD_LOGIC

                                             vh_basetype=STD_ULOGIC

                                             vh_converter=E2STD_LOGIC

                                             vh_vectortype=STD_LOGIC_VECTOR

Examples

In the following example, the analog_top.cir file contains the subcircuit definition for ANALOG_top. The portmap statement tells the elaborator not to map Verilog buses to SPICE ports (autobus=no) and not to change the case mappings between Verilog-AMS instantiations and SPICE subcircuits (casemap=keep). The config statement tells the elaborator to bind the ANALOG_top cell as a SPICE subcircuit; the analog_top.cir file contains the master.

include "analog_top.cir" // SPICE or Spectre format include file amsd{ portmap subckt=ANALOG_top autobus=no casemap=keep config cell=ANALOG_top use=spice }

The following example shows how you can specify a custom port-bind file for a Verilog-SPICE boundary:

amsd{ portmap subckt=analog_top file=top.pb config cell=analog_top use=spice }

The following example shows how you can specify a custom port-bind file for a SPICE-in-the-middle design unit:

amsd{ portmap module=nand2 file=nand2.pb config inst=top.a1.x1 use=hdl }

The following example illustrates using a reference file for a SPICE-in-the-middle construct. Note that the default value of porttype (for the reference file) is order:

amsd{ portmap subckt=analog_spice reffile=analog_spice.v autobus=yes config cell=anglog_spice use=spice portmap module=nand2 config cell=nand2 use=hdl }

The following example shows how you might specify customized port bindings for a SPICE-on-leaf construct using a reference file:

amsd{ portmap subckt=analog_spice reffile=analog_spice.v autobus=yes config cell=anglog_spice use=spice }

Here are some more examples:

amsd{ portmap subckt=ana_gate reffile=ana_gate.v refformat=verilog config cell=ana_gate use=spice portmap module=nand2 file=nand2.pb config cell=nand2 use=hdl }

amsd{ portmap subckt=pll_top busdelim=_ file=pll_top.pb config cell=pll_top use=spice portmap module=divider file=divider.pb config cell=divider use=hdl portmap module=counter file=counter.pb config cell=counter use=hdl }

SPICE Port-to-Verilog Bus Mapping Example

Verilog in file top.v:

module pll_top(refclk, p0_clk, reset);
wire [1:0] p0_clk;
...
endmodule

module top;
...
pll_top p1(...);
...

Spice-to-Verilog Port Mapping

Examples

SPICE Port-to-Verilog Bus Mapping Example

Related Topics