Implicit and Explicit Port Mapping

Depending on the design structure and your port mapping requirements, you can apply port mapping inside an amsd block in two ways:

• Implicit portmap: For SPICE-in-Middle and SPICE-on-Leaf design flows in Verilog-AMS, port mapping can be achieved without using the portmap statement. Only the config statement would suffice. The tool automatically generates implicit portmaps, with default values, for the subcircuits or modules referred to in the configcard. In the autogenerated portmap statement, the cell name used in the config statement is used as the SPICE subcircuit name or the Verilog module name, and the default values are be assumed for all other parameters of the portmap statement.
  
  Examples

  • If the config statement is config cell=divider use=hdl, the following portmap statement would be autogenerated.
    portmap module=divider

  • If the config statement is config cell=analog_top_a use=spice, the following portmap statement would be autogenerated.
    portmap subckt=analog_top_a

The tool assumes the following portmap parameter default values for autogenerating skeletons, commfile, or the portbind file: autobus=yes
busdelim="[] <>"
refformat=verilog
interconnect=mixed

• Explicit portmap: In most situations, portmap and config statements are required in pairs to specify cell bindings. One pair of portmap and config statements can bind multiple instances of the same cell to either a SPICE port in a Verilog block or a Verilog port in a SPICE block.

          Example
     portmap subckt=foo autobus=yes portcase=lower busdelim=_ refformat=verilog
     config inst="top.inst1 top.inst2 top.inst3" use=spice
           Here, inst1, inst2, and inst3 are instances of foo in the Verilog module top, which needs to be configured to SPICE.

Related Topics

• portmap
• Spice-to-Verilog Port Mapping
• SPICE