Product Documentation
Virtuoso ADE Assembler User Guide
Product Version IC23.1, November 2023

9


Netlisting

The environment generates the following files for simulation:

File Description

Netlist

Contains component and design connectivity information only

Simulator input file

Contains the netlist and simulator control information

The environment passes the simulator input file to your configured simulator.

ADE Assembler creates or updates the simulator input file automatically when you give the command to run a simulation. The environment creates hierarchical netlists incrementally: incremental netlisting is faster than full hierarchical netlisting because the environment updates the netlist only for those schematics that have changed since it created the previous netlist.

Alternatively, you can generate a netlist and simulator input file when

See the following topics for more information:

Creating a Netlist

Displaying a Netlist

To display an existing simulator input file, do one of the following:

Expanding Hierarchy to Netlist a Design

While netlisting a hierarchical design, the environment expands every cell (instance) into lower level cells until it reaches one designated as a primitive. The environment adds each primitive to the netlist.

At each level in your design hierarchy, you can have one or more views for each cell. You use a view list to specify which view the design environment selects for expansion during netlisting. View lists can be global to the entire design or specific to an instance as specified by its property values.

For analog simulation, you specify the global or default view list in the Switch View List field of the Environment Options form when the selected cellview is not a configuration (config) view. If an instance does not have any of the views listed in the switch view list, the netlister reports an error.

The netlister uses the stop list, which you specify in the Stop View List field on the Environment Options form, to identify primitives. When the netlister reaches a view that is specified in both the switch and the stop list, it netlists the instance and does not expand beyond this level.

If you are using DSPF subcircuits that contain blackboxes, the netlister traverses inside each blackbox device and uses the schematic name corresponding to each object to write the save statement in the netlist. This helps in probing the device terminals or objects inside the blackbox devices.

Parasitic simulation and mixed-signal simulation use different processes for creating switch and stop view lists. See the Virtuoso Parasitic Aware Design User Guide and the Virtuoso Mixed-Signal Circuit Design Environment User Guide for more information.

The following flowchart shows how a typical OSS-based netlister netlists a design.

The following figure illustrates how hierarchy expansion is performed on a simple design. The solid lines show the view selection and design expansion based on the switch view list and stop view list shown.


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