Working with Buses in OpenAccess

While using the Abstractor Generator tool for bus terminals, use the following options before running the tool:

( absSetOption( "AnnotateBusInAbstract" "true"))

You need to run verilogAnnotate after running Abstractor Generator (with the above settings) to set the interface bit for each valid logical term in the cells. If you fail to run, you will get the following error while running saveDesign -cellview.

*ERROR: (IMPOAX-683): Unable to find module terminal "D" for module "JACK". Can not create Connection Data for this terminal.

• If you are running assembleDesign on AMS blocks created in Virtuoso, verilogAnnotate needs to be run on the layout views (or the view name being used for assembleDesign) besides abstract views.

• If you use VLS-XL to generate layouts, set the following and you can ignore bus annotation during abstract generation flow: 
  envSetVal("layoutXL" "createImplicitBusTerminals" 'boolean t)

12.2 The Interface Bit Setting of a Terminal

To preserve the logical connectivity of a terminal to the corresponding net, the terminal of the block/cell must have the isInterface bit set to true. 

The following examples depict what can happen when the interface bit is not properly set:

Example 1 - isInterface of both the bus and its individual scalar terminals is set to true

Consider a design in which the isInterface attribute of both the bus, such as main_bus<1:0>, and its individual scalar terminals, such as main_bus <1> and main_bus <0>, is set to true. In this case, you may encounter an error with the following message during the assembleDesign step in Innovus:

Duplicate Fterms are encountered

To resolve the problem, run verilogAnnoate to turn off the isInterface attribute of both scalar terminals.

Example 2 - Some terminals in the block/cell do not have isInterface set to true during partitioning

Consider a situation in which some of the terminals in the block/cell do not have the isInterface bit set to true during the partitioning of a design. In this case, these terminals will have issues when the block is being assembled with the top level. 

The isInterface bit is meant to align with the Verilog modules. So, if an OpenAccess abstract terminal has isInterface = nil, it should not appear in the Verilog netlist when running saveNetlist, unless the -includePowerGround or -phys options are used. Terminals with isInterface = nil should be connected only to a USE POWER/GROUND net, not a regular signal net. Assuming that the Verilog module (and .lib) has port, running verilogAnnotate will set the bit on the abstract's terminal to true instead of nil.

To fix this problem, run the verilogAnnotate command on the layout view of the cell or recreate the reference libraries with the interface bit set for this terminal.

12.2.1 Checking for the Presence of the Interface Bit

Before moving to the Innovus flow, you may want to check that certain terminals carry these interface bits. To do so, run oaDBChecker and check the log file for INFO such as the following:

Checking for status of interface bit for all blocks in the current view...
INFO (CHECKER_DESGN-14): Interface bit on terminal 'cntrlyo<7>' of cell 'dtmf_chip' is set to false.

Note: If the original Virtuoso DB was created using Virtuoso-L, the isInterface bit could be set to true on the Bus terminal as well as the scalar terminals. This might be okay with Virtuoso but Verilog does not support this configuration in Innovus. Run verilogAnnotate to resolve this issue as mentioned in the previous section.

12.2.2 Running verilogAnnotate

Run verilogAnnotate as follows:

verilogAnnotate -refLibs libraryList -verilog fileList [Optional_Arguments]

Example

restoreDesign -cellview {lib cell view}

# If you have only the top-level design netlist but not the specific cell's netlist, you first need to generate a leaf-only netlist as follows:

saveNetlist leafOnly.v -onlyLeafCell

# Make sure you have write permission to update the OpenAccess file:

verilogAnnotate -refLibs library_1 -verilog leafOnly.v

exit

#Restart the tool

restoreDesign -cellview {lib cell view}

attachTerm ...

saveDesign ...

The saved design will have the changes saved.