Contents

About This Manual

Audience

How to Use This Document

Related Documents

Innovus Product Documentation

Innovus Stylus Common UI Product Documentation

Virtuoso Documentation

1

Getting Started

1.1 Product and Installation Information

1.2 Setting the Run-Time Environment for Innovus

1.2.1 Supported and Compatible Platforms

1.2.2 64-Bit Version of Innovus Applications

1.3 Temporary File Locations

1.4 OpenAccess

1.5 Launching the Console

1.6 Accessing Documentation and Help in Innovus

1.6.1 Launching Cadence Help From the Command Prompt

1.6.2 Using the Innovus man and help Commands on the Text Command Line

1.7 Starting the Virtuoso Studio Design Environment

1.8 Innovus and Virtuoso Release Compatibility Information

2

Overview of Mixed Signal Interoperability

2.1 Mixed Signal Solution - Introduction

2.1.1 Design Methodologies Supported by the Cadence Mixed Signal Solution

3

Technology Data Preparation

3.1 Software Requirements

3.2 Technology Data Preparation

3.2.1 Library and Technology Requirements

3.2.2 Preparing the Technology Library

3.2.3 Determining Whether Your MSOA PDK Is Traditional or Rapid

3.2.4 Preparing the IP Library

3.2.5 Creating a Rapid MSOA PDK with Multiple foundry_innovus Constraint Groups

3.2.6 Preparing a Technology Library with Multiple LDRSs

3.2.7 Rapid PDK ASCII Techfile Structure

4

Design Data Preparation

4.1 Special Settings/Instructions To Enable the Mixed-Signal Flow

4.2 Name Space Mapping in the OpenAccess Interoperable Flow

4.3 Converting an Existing LEF/DEF-based Design into OpenAccess

4.3.1 Converting a LEF/DEF-based design into OpenAccess by using oaOut

4.4 Migrating a LEF and Floorplan File-based Flow to OpenAccess

4.5 Running Innovus in the OpenAccess Mode

4.5.1 Initializing Innovus for Implementing a Digital Block in OpenAccess

4.5.2 Initializing Innovus with the OpenAccess Database of a Design Created in Virtuoso XL

4.6 Interoperability of Constraint Groups and Non-Default Rules between Virtuoso and Innovus

4.7 Generic Guidelines To Run the Netlist-Driven Mixed-Signal Flow

5

Schematic-Driven Mixed Signal Design Flow

5.1 Schematic-Driven Mixed Signal Flow

5.1.1 Overview

5.1.2 Top-Level Early Floorplanning 

5.1.3 The Analog Block Implementation Sub-Flow

5.1.4 Custom Digital Implementation Flow

5.1.5 Digital Block Implementation Flow

5.1.6 OpenAccess Based Interoperable Flow between Innovus and Virtuoso

5.1.7 Top-Level Block/Chip Assembly flow

5.1.8 Virtuoso Top-Level Assembly

5.1.9 Virtuoso Chip-Level Layout Assembly

5.2 Flow Example: Power PushDown Flow for Digital Blocks in AoT Designs

5.2.1 Performing Top-Level Floorplanning in Virtuoso

5.2.2 Pushing Power Shapes into the Digital Block

5.2.3 Implementing the Digital Block in Innovus

5.2.4 Bringing Back the Digital Block into Virtuoso for Design Assembly

6

Virtuoso Digital Implementation

6.1 Overview

6.2 Invoking the VDI Environment

6.2.1 Starting Innovus Using a Verilog Netlist

6.2.2 Starting Innovus Using an OpenAccess Database from Virtuoso

6.2.3 Starting Innovus Using an Existing Script

6.2.4 Loading Existing Form Configuration

6.3 Configuring Power Planning and Power Routing

6.4 Creating the View Definition File

6.4.1 Implementing a Digital Block in the Single Timing Analysis Mode

6.4.2 Implementing a Digital Block in the BcWc or Min/Max Analysis Mode

6.4.3 Implementing a Digital Block in the MMMC Analysis Mode

6.5 Specifying Physical Cells

6.6 Specifying Optional Plugin Scripts

6.7 Generating the Innovus Script

6.7.1 With Customization

6.7.2 Without Customization

6.8 Completing the Implementation

6.9 Sample Files

6.9.1 Sample View Definition File

6.9.2 Sample SDC File

6.9.3 Generated Innovus Script Sample

6.10 Helpful Hints

7

Quick Abstract Inference

7.1 Overview of Quick Abstract Inference

7.2 Why Abstracts Are Still Required for Standard Cells

7.3 How QAI Works

7.3.1 Rules for Abstract Inference

7.3.2 Detailed Description of Data Objects

7.3.3 Blockage Modeling in QAI

7.3.4 QAI Pin Modeling

7.3.5 Antenna Annotation Utility for Creating Accurate Antenna Information for the Innovus Flow

8

Netlist-Driven Mixed Signal Design Flow

8.1 Overview

8.2 Technology and IP Library Preparation

8.3 Verilog Netlist Creation

8.4 General comments

8.5 Floorplanning 

8.5.1 Floorplanning of Verilog Netlist Using Blackboxes

8.5.2 Generate From Source for Soft Analog Block Layout Using Virtuoso

8.5.3 Load Physical View to Merge Optimized Pin Locations and Block Boundary

8.5.4 Physical Implementation of Soft Analog Blocks Using Virtuoso

8.5.5 Physical Implementation of Soft Digital Blocks Using Innovus

8.6 Top-level Analog Net and Power Routing

8.7 Top-level Design Implementation

8.8 Final Chip Integration and Sign-Off

8.9 ECO Flows

9

OpenAccess Wiring Terminology

9.1 Creating an Interoperable Digital Block Floorplan in Virtuoso Layout Suite XL

9.2 Understanding Symbolic and Geometric Routing

9.2.1 Differences Between Symbolic and Geometric Routing

9.2.2 Identifying Symbolic Routing and Geometric Routing

9.2.3 Identifying the Route Status for Symbolic and Geometric Routing

9.2.4 Ways of Creating Wires in Virtuoso and Innovus Environment

9.3 Locking a Net Using Virtuoso Space-Based Router (VSR)

9.3.1 Locking a partially routed net

9.3.2 Locking a net that is completely unrouted

9.3.3 Locking a completely routed net

9.3.4 Unlocking Nets

9.3.5 Highlighting Locked Nets

9.4 Editing Net Attributes in Virtuoso

9.5 Wire/Net Mapping Between Virtuoso and Innovus

9.6 Handling of Wires from Virtuoso in Innovus

9.6.1 Conversion of Wires to DEF SPECIALNETS in Innovus

9.6.2  Implications of the Conversion in Innovus

9.6.3 Addressing the Conversion Issue

9.6.4 How To Prevent the Conversion Issue

9.7 Wiring Connectivity in Innovus

9.8 Wiring Extraction in Innovus

10

Trim Metal Interoperability

10.1 Introduction to Trim Metal

10.1.1 The TRIMMETAL LAYER

10.1.2 General Requirements for N7, N5, and N3 Designs

10.1.3 What Is Trim Metal?

10.2 Technology Requirements for Trim Metal Insertion

10.3 Trim Metal Insertion Flow in Virtuoso

10.3.1 Trim Shape Rules

10.3.2 Trim Shape Extension Models

10.4 Supporting Tool Enhancements

11

Routing Constraint Interoperability

11.1 An Overview of Routing and Constraint Interoperability

11.2 Steps for Creating an Interoperable NDR in Virtuoso

11.3 Creating Interoperable Shielding Constraints in Virtuoso

11.4 Routing Constraints Understood by NanoRoute (Digital Router in Innovus)

11.5 Creating/Viewing Interoperable Routing Constraints in Virtuoso

11.5.1 Creating Interoperable Constraints Using Virtuoso Constraint Manager

11.5.2 Checking OpenAccess Database with Constraints Prior to Bringing a Design into OA DB Checker System

11.6 Creating Interoperable Routing Constraints Using Innovus

11.7 Hierarchical Propagation of Constraints

11.8 Creating/Adding Mixed-Signal Routing Constraints on IP Blocks

11.9 Routing Constraints Interoperability between NanoRoute and VSR

11.9.1 Getting a List of Nets with skip_routing Attribute

11.9.2 Checking Routing Results Against the Routing Constraints

11.9.3 Creating Interoperable Library between Innovus and Virtuoso

11.10 Trying the Constraint Interoperability Environment and the run_vsr Command in Innovus for the First Time

12

Working with Buses in OpenAccess

12.1 Settings for Automatic Annotation of Bus Bits During Abstract Generation using Virtuoso Abstract Generator

12.2 The Interface Bit Setting of a Terminal

12.2.1 Checking for the Presence of the Interface Bit

12.2.2 Running verilogAnnotate

13

High Frequency Router In Innovus

13.1 Overview

13.2 Invoking NRHF

13.3 Controlling NRHF Routing

13.4 Supported Routing Styles

13.4.1 Non-default Routing

13.4.2 Shielding

13.4.3 Differential Pair

13.4.4 Match Length

13.4.5 Resistance Match

13.4.6 Layer Match

13.4.7 Bus Routing

13.4.8 Length Control

14

Working with Vias in OpenAccess

14.1 Overview

14.2 Types of Via Definitions

14.2.1 Custom Vias or customViaDefs

14.2.2 VIARULE or standardViaDefs

14.2.3 standardViaVariants

14.3 How Tools Find and Use Vias

14.3.1 generateVias

14.3.2 Summary Table

14.3.3 cdsFixedVias

14.4 Examples

14.4.1 Setting the LDRS in Virtuoso Layout Suite

14.4.2 Checking Vias in the Tech File

14.5 Directing the Router to Use Only the Vias in the ITDB in Innovus

15

Placing Standard-cell-based Designs from Virtuoso

15.1 Overview

15.2 Guidelines for Placing a Standard-cell-based Design from Virtuoso in Innovus

15.3 What are Sites and Rows in Innovus and Why They Are Needed

15.4 Site Property in the Cell View of Standard Cells

15.5 Site Definition in the Technology Library

15.6 Standard Row Creation by Innovus During init_design

15.7 Switching the Orientation of the Standard Rows

16

Using NanoRoute To Route a Design from Virtuoso

16.1 Overview

16.2 What Are Routing Tracks?

16.3 Guidelines for Using Innovus To Route a Design from Virtuoso

16.4 Interoperability of Routing Tracks

16.4.1 Supported Use Models for the Interoperability of Routing Tracks

16.4.2 Role of add_tracks in the Interoperability of Routing Tracks

16.4.3 Role of setOaxMode -updateMode in the Interoperability of Routing Tracks

16.5 Track Alignment in Innovus

16.5.1 Relationship Between Wire Width, Routing Track Pitch, and Minimum Spacing Requirement

16.5.2 Alignment of I/O Pins with Routing Tracks

16.5.3 Alignment of I/O Pins with Non-Uniform-Pitch Tracks in Lower Technology Nodes

16.5.4 Access to I/O Pins with Double Patterning Layers in Lower Technology Nodes

16.5.5 Access to Standard-Cell I/O Pins in Lower Technology Nodes

16.5.6 Access to Standard-Cell I/O Pins with Double Patterning Layers

16.5.7 Track Patterns with Non-Uniform Pitch

16.5.8 Track Patterns with Non-Uniform Pitch and Non-Default Width

17

Design and Core Boundary in Innovus

17.1 Design and Core Boundary Definitions

17.2 Matching the Orientation of Rows and Standard Cells

17.3 Handling Gaps Between Standard Cells and the Design Boundary

17.3.1 Gap Between the Left Edge of the Leftmost Standard Cell and the Design Boundary

17.3.2 Gaps Between the Left and Bottom Edges of Standard Cells and the Design Boundary

17.4 Creating Double-Height Rows

17.5 Creating Routing Tracks with Respect to coreBox

17.6 Resizing the PRBoundary Object in Virtuoso

18

Static Timing Analysis for Mixed Signal Designs

18.1 Overview

18.2 OpenAccess Compatibility for Mixed-Signal STA Flow

18.2.1 Basic Design Requirements

18.2.2 Requirements for Correct Connectivity Propagation

18.2.3 Requirements for OpenAccess Compatibility

18.2.4 Useful Utilities and Information

18.3 Handling Schematic-Driven Designs Implemented Using a Non-Interoperable PDK

18.3.1 Checking the Technology Database Graph of a Specific Design Library

18.3.2 Opening a Design Attached to a Non-Interoperable PDK in Innovus

18.3.3 Ways To Switch a Design Library from a Non-Interoperable to an Interoperable PDK

18.4 Running STA by Flattening the Design

18.4.1 Steps for Running STA Using the Flatten Approach

18.5 Running STA by Using the FTM

18.5.1 Generating the FTM for Each Block

18.5.2 Running STA on Top-level Design with FTM of Blocks

18.6 Difference between Flat and FTM Approaches

18.7 Guidelines for Running STA Flow on Mixed-Signal Design

18.8 Creating a Quick Timing Model for Analog IPs in Innovus

18.9 Different Ways of Running assembleDesign

18.9.1 Running assembleDesign in the Batch Mode

18.9.2 Running assembleDesign in the Incremental Mode

18.9.3 Differences between the Batch and Incremental Modes of assembleDesign

18.9.4 Running assembleDesign with the -allTimingBlocks Option

18.9.5 Tips on Running assembleDesign -allTimingBlocks

18.9.6 Caveats for and Limitations of assembleDesign -allTimingBlocks

18.9.7 Running assembleDesign in the Batch Mode and Subsequently in the Incremental Mode

18.9.8 Limitations of assembleDesign

18.10 Parasitic RC Extraction for Running MS-STA

18.10.1 Running Quantus Extraction with postRoute Engine for a Routed Design

18.10.2 Running Quantus Extraction with Signoff Effort Level

18.10.3 Using the Quantus Layer Map File

18.10.4 Auto-creation of the Quantus Layer Map File from Innovus

18.10.5 Running Signoff Quantus Extraction in the OpenAccess Mode

18.10.6 Auto-creation of Input Files from Innovus To Run Standalone Quantus QRC

18.10.7 Running Standalone Quantus QRC and Loading the Resulting SPEF Files Back to Innovus

18.11 Tips for Debugging the No Constrained Timing Path Issue Generated by report_timing

18.11.1 Case Studies

18.11.2 Basic Conditions for Reporting the Timing on a Path

18.11.3 Common No Constraint Situations

18.11.4 Checking the Validity of a Timing Constraint

18.11.5 Checking the Existence of a Design Object in the Layout

18.11.6 Common Invalid Timing Path Situations

19

Chip Finishing and ECO Flows

19.1 Overview

19.2 Virtuoso-Based ECO Flow

19.3 Innovus-Based ECO Flow

19.3.1 Overview

19.3.2 Pre-Mask ECO Flow Steps

19.3.3 Post-Mask ECO Flow Steps

19.3.4 Example Post-Mask ECO Scenarios

20

OpenAccess Database Interoperability Checker

20.1 Overview

20.2 Running the OA DB Checker

20.3 Check Library - Innovus Interoperability Library Checker

20.3.1 Technology DB Checker

20.3.2 Library DB Checker

20.3.3 Check Pins between Two Cellviews for the Remaster Instance

20.3.4 Report File Name

20.4 Check Design - Innovus Interoperability Design Checker

20.4.1 CellView(s)

20.4.2 Report File Name

20.4.3 Checks

20.5 Create Check File - Create Check Design File

20.6 Viewing OA DB Checker Violation Markers in the Annotation Browser in Virtuoso

20.7 Run Innovus - Innovus Launch GUI

20.8 OA DB Checker Use Case Scenarios for Virtuoso Users

21

oaZip Utility

21.1 The oazip Utility to Compress/Decompress Databases

21.1.1 Command Syntax

21.1.2 Arguments

22

Voltage Dependent Rule Interoperability

22.1 Overview

22.2 VDR Syntax

23

Useful Tips

23.1 Removing Pipe Character from Instance Names

23.2 Viewing PCells in Innovus

23.3 Global Net Name Collision Resolution

23.4 NanoRoute Support for Nets

23.5 Saving Blackboxes in OpenAccess

23.6 Importing the Power and Ground Nets Connections Using Verilog Netlist

23.7 Turning Off Power and Ground Connections in a Netlist

23.7.1 verilogAnnotate Command Syntax

23.8 Generating Power and Ground Pins

23.9 Using Abstract Views in Innovus

23.10 Performing Power Routing Outside Innovus

23.11 Generating Abstracts with Antenna Information

23.12 Mapping Virtuoso Bind Keys to Innovus Bind Keys

23.13 SKILL to TCL Mapping

23.14 Generating a Verilog Netlist for Innovus from a Virtuoso Schematic

23.14.1 Netlisting Options

23.14.2 Schematic and Hierarchy Editor Setup

23.14.3 Netlist Generation

23.14.4 Problems and Solutions

23.14.5 Filtering Power and Ground Nets in Verilog

23.14.6 Netlisting Options

23.14.7 Schematic Modifications

23.14.8 Limitation due to Split Bus and Bundle with `Merge All'

23.15 Creating a Non-Default Rule in Virtuoso and then Using it in Innovus

23.15.1 Using Virtuoso

23.15.2 Using Innovus

23.16 Troubleshooting Common Errors in Innovus OpenAccess Flow

23.16.1 IMPOAX-717 Error

23.17 Working with Old Versions of OpenAccess Data