vhdlPinListToVHDL

vhdlPinListToVHDL(
t_libName
t_cellName
t_viewName
l_pinList
)
=> t / nil

Description

Allows the generation of VHDL views from an intermediate pin list format.

The pinList has the following format:

( ports (nil name "termName" direction "termDir"
    pins ( (name "pinName" accessDir "pinAccessDir"
            pinPropName pinPropValue ...)
            .   .    .   .   .   .   .   .   .
            (name "pinName" accessDir "pinAccessDir"
               pinPropName pinPropValue ...)
               
                prop (termPropName termPropValue ...)
             
            .   .   .   .   .   .   .   .   .   .   .   .   .
         .   .   .   .   .   .   .   .   .   .   .   .   .
         .   .   .   .   .   .   .   .   .   .   .   .   .
         (nil name "termName" direction "termDir"
            pins ( (name "pinName" accessDir "pinAccessDir"
                     pinPropName pinPropValue ...)
                      .    .   .   .   .   .   .   .
                     (name "pinName" accessDir "pinAccessDir"
                     pinPropName pinPropValue ...)
                      
            prop (termPropName termPropValue ...)
            
         prop (nil cvPropName cvPropValue ...)
         
    Returns
      t if successful
        else nil
        )

Arguments

t_libName	The name of the library to store the VHDL cellview.
t_cellName	The cell name of the translated VHDL cellview.
t_viewName	The view name of the translated VHDL cellview.
l_pinList	The pin list to be translated to the VHDL cellview

Value Returned

t	The VHDL view is generated.
nil	The command was unsuccessful.

Examples

Related Topics

vhdlHiImport

vhdlImport

vhdlRegisterSimulator

vhdlToPinList

Verilog In and VHDL In Import Functions

Return to top