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Verilog In and VHDL In Import Functions

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This manual is intended for designers who want to use Verilog and VHDL files in designs maintained in the Virtuoso Studio design environment.

This topic describes the SKILL functions used to import HDL files into the Virtuoso^® design environment and to convert netlists to schematic diagrams.

• Verilog In Function - Virtuoso Verilog In lets you convert structural Verilog netlists into one of the following forms:
  • Virtuoso schematics
  • Netlists in Cadence OpenAccess format
  • Verilog text views in a Cadence-format library
  
  In each case, the design is converted into a data format that can be used by Cadence® tools. The following SKILL function lets you access the Verilog In tool:
  • impHdlDisplay
• VHDL In Functions - Virtuoso VHDL In lets you convert a VHDL structural or behavioral description into one of the following types of views:
  • Schematic view
  • Netlist view
  • VHDL text views
  
  In each case, VHDL In imports the design from the VHDL format into Virtuoso database format, a data format that can be used by Cadence tools. You can import the following into a Virtuoso library:
  • VHDL designs
  • VHDL ASIC libraries
  • VHDL designs, minus modules that already exist in the Virtuoso® Design Environment library
  • Pieces of a hierarchical design
  • A combination of the above architecture
  
  The following SKILL functions let you perform various tasks using the VHDL In tool:
  • vhdlHiImport
  • vhdlImport
  • vhdlPinListToVHDL
  • vhdlRegisterSimulator
  • vhdlToPinList

Licensing Requirements

For information on licensing in the Virtuoso Studio design environment, see the Virtuoso Software Licensing and Configuration User Guide.

Related Topics

Getting Started with VHDL In

Using Verilog In

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