vhdlToPinList
vhdlToPinList(
t_libName
t_cellName
t_viewName
)
=> list / nil
Description
Translates a VHDL cellview into an intermediate pin list format.
Arguments
|
t_libName
|
Name of the library containing the VHDL cellview.
|
|
t_cellName
|
Cell name of the VHDL cellview to be translated.
|
|
t_viewName
|
View name of the VHDL cellview to be created.
|
Value Returned
|
list
|
The pin list.
|
|
nil
|
The command is unsuccessful.
|
The pin list is returned in the following format:
|
l_pinList
|
A DPL list describing the cellview ports, cellview properties, and port properties in the following format:
|
|
<l_pinList>
|
(nil ports <portList> [props <propList>]
|
|
<portList>
|
(<port> [ <portList> ] )
|
|
<port>
|
(nil name "termName" direction "termDir"
|
|
|
[prop <propList>] [pins <pinList>] )
|
|
<propList>
|
(<prop> [ <propList> ] )
|
|
<prop>
|
(nil s_propName t_propValue s_propName t_propValue )
|
|
<pinList>
|
(<pin> [ <pinList> ] )
|
|
<pin>
|
(nil name "pinName" accessDir "pinAccessDir" [prop <propList>] )
|
Examples
pinList =
list(nil
'ports list(
list(nil 'name "clock" 'direction "input")
list(nil 'name "a0" 'direction "output"
'prop list(nil 'delay 55.0))
)
'prop list(nil 'partName "count" 'myProp 5)
)
Related Topics
vhdlHiImport
vhdlImport
vhdlPinListToVHDL
vhdlRegisterSimulator
Verilog In and VHDL In Import Functions
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