Product Documentation
SpectreVerilog/UltraSimVerilog Migration to AMS Designer
Product Version IC23.1, June 2023


Contents

1

Setting Up the Migration Example

Features of the Migration Example

Testbench for the PLL Design

Inside the PLL_160MHZ Instance

2

Using the Spectre AMS Designer Simulator

Changing the Simulator to AMS Designer

Loading the State File for AMS Designer

Selecting and Customizing Connect Rules for AMS Designer

Setting Netlister and Run Modes

Viewing Options

Viewing Analog (Spectre) Options
Viewing FastSPICE (UltraSim) Options
Viewing AMS Options

Netlisting and Running

Viewing Waveforms

Displaying Partitions

Understanding Connect Rules and Disciplines in AMS Designer

Simulating the Design Using the Spectre Solver


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