Product Documentation
Virtuoso NC-Verilog Environment User Guide
Product Version IC23.1, September 2023

2

NC-Verilog Integration Control Commands

This chapter describes the commands and forms you can use from the Virtuoso® Verilog Environment for the NC-Verilog Integration window.

About the Main NC-Verilog Window

The Virtuoso® Verilog Environment for the NC-Verilog Integration window (main NC-Verilog window) gets displayed when you first enter the NC-Verilog Integration Environment. The main NC-Verilog window provides access to simulation commands, command forms, and support tools.

The following figure shows the main NC-Verilog window:

The main NC-Verilog window sections include the status line, menu banner, fixed menu, Run Directory field, Top Level Design selection fields and Simulate Options fields.

Status Line

The Status Line shows the current operating mode of the current design. The following figure shows the Status Line:

Menu Banner

The Menu Banner lets you access all the commands, forms, and tools required for controlling the simulation with the help of the following set of options:

Fixed Menu

The Fixed Menu provides access to the frequently used commands. For more information on its options, refer to Fixed Menu.

Run Directory

The Run Directory field is used to specify the name of the directory for design netlisting, simulation and waveform database creation. You can specify a new or already existing directory name in this field. For more information, refer to Initializing a Design.

Top Level Design Options

Use the Top Level Design options to specify the Library, Cell and View name of the top level design.

Once you specify any run directory name or top level library, cell or view name you need to press the tab key for the system to accept that value and move to the next field. Alternatively you can also click the next field after you have entered the value for one of the fields.

Simulate Options

Simulator Mode specifies the kind of simulation that you require. It can be either Interactive or Batch.

The executable and log file names will depend on the simulator being used. For the changes in the executable and log file name when using the Xcelium simulator, see Running Simulations with Xcelium.

Commands Menu

Setup Menu

The following tables describe the below mentioned Setup menu options:

SDF Delay Annotation

Selecting this option displays the SDF Delay Annotation Setup form. In this form, you can specify an SDF delay file to be prepared for ncelab to annotate. The SDF delay file will be converted from the Virtuoso Design Editor L name space to Verilog name space by running sdf2sdf3 (this is an optional feature). After this, it is compiled using ncsdfc. Next, the compiled SDF file is stored in the run directory under the name <Original SDF File Name>.compiled. Finally, an SDF command file will be created which will then be passed on to ncelab during elaboration time.

Setting the Delay Annotation Options

The following table describes the various delay annotation options:

SDF Delay Annotation Options

Options Description

Suppress SDF CellType Checking

Suppresses the CellType mismatch checking performed by NC-Verilog SDF backannotator. When enabled (default), “+sdf_nocheck_celltype” is sent to NC-Verilog.

Suppress sdf2sdf3 Running

Suppresses the sdf2sdf3 process when you start a simulation. When selected, the simulator reads the sdf2sdf information from the last simulation.

You must run the sdf2sdf3 process at least once to create an sdf2sdf file. When you run sdf2sdf3, you must complete the SDF Scope field. When the simulator does not find an sdf2sdf file, an error message appears.

Suppress sdf2sdf3 Warning Message

Suppresses warning messages generated by sdf2sdf3. When enabled, a -nowarn is sent to sdf2sdf3.

Delay File

It is a n SDF file used to backannotate your design. If the file is in the current directory, you enter the filename. If the file is in a different run directory, you enter the full path.

sdf2sdf File

Stores information generated by the sdf2sdf3 process. When you run the sdf2sdf3 process, the simulator writes information to the file specified in this field. When you suppress the sdf2sdf3 process, the simulator reads information from the file specified in this field.

SDF Scope

Specifies the scope you want the system to preappend to the sdf2sdf file. You must complete this field when you run sdf2sdf3 process.

SDF Module Instance

Specifies the module that the SDF file annotates. You do not specify this option when backannotating an entire design.

Delay Config File

Specifies an annotator configuration file. An annotator configuration file contains commands that let you control backannotation. Refer to the SDF Annotator User Guide for more information.

Log File

Specifies a log file other than the default sdf.log file. The log file stores the warning, error, and informational messages generated when you run sdf2sdf3.

Use Delay Type

Specifies which of the three delay types (Minimum, Typical, or Maximum) to use for annotation. The delay type is derived from the SDF file unless you specify another source with the Tool Control or From Config options (see below).

  • Tool Control takes the delay type from the Simulation Options form (Refer to the Setup – Simulation command).
  • Minimum takes the minimum delay value from the SDF file.
  • Typical takes the typical delay value from the SDF file.
  • Maximum takes the maximum delay value from the SDF file.
  • From Config takes the delay value from the delay type specified in the Delay Config File field.

Delay Scaling

Enables you to factor the value of delay types. To apply these options to your simulation, you must select a delay type from the Use Delay Type field described above.

Scale Source Delay

It is the delay type whose value is factored by the Scale Factor options.

  • Min_Typ_Max takes the minimum, typical, and maximum values from the SDF file.
  • Minimum takes the minimum delay value from the SDF file.
  • Typical takes the typical delay value from the SDF file.
  • Maximum takes the maximum delay value from the SDF file.
  • From Config takes the delay type from the Delay Configuration file.

Scale Factor

Specifies multipliers for the Scale Source Delay value. You enter real number multipliers in the Minimum, Typical, and Maximum fields.

  • From Config applies scale factors supplied in the Delay Configuration file.
  • Minimum is the factor by which NC-Verilog scales the minimum value for each delay.
  • Typical is the factor by which NC-Verilog scales the typical value for each delay.
  • Maximum is the factor by which NC-Verilog scales the maximum value for each delay.
You can enter scaling instructions in the annotator configuration file that you specify in the Delay Config File field described above.
The Use Delay Type, Scale Source Delay, and Scale Factor options are used to determine the delays annotated to the Verilog design for simulation. See the example that follows.

Example of Determining Delays

The following sample shows an SDF delay entry for a timing path from A to Z. 

SDF Delay File: (IOPATH A Z (2:3:5))

The scaling example is based on the following delay annotation settings:

Scale Source Delay:    Maximum
Scale Factor:       Minimum = .5, Typical = 1,    Maximum = 2
Use Delay Type:    Minimum

The simulator uses the following process to scale the delays and to determine which single delay is annotated for simulation:

  1. The Scale Source Delay setting specifies to use the maximum delay in the SDF file as the initial value for scaling Minimum, Typical, and Maximum delay values.
  2. The initial value multiplied by the factor value results in the scaled delay value, as shown in the following table.
    Minimum Typical Maximum

    (Multiplicand)

    Initial Value

    5

    5

    5

    (Multiplier)

    Factor Value

    0.5

    1

    2

    (Product)

    Scaled Delay Value

    2.5

    5

    10
  3. The Use Delay Type setting specifies which scaled delay to annotate to the simulation. In the sample setting, Minimum is specified.
  4. The value of 2.5 is annotated to the simulation.

Netlist

Selecting this option displays the Netlist Setup form. You use this form to specify options for the design to netlist and the views to netlist.

The following tables describe how the netlisting options affect netlisting.

Specifying the Netlisting Mode

Option Description

Entire Design

Netlists your entire design regardless of which cells have been modified since the last netlist was generated.

Incremental

Netlist only those parts of the design that have changed since the last netlist was generated.

Off

Does not generate netlist of your design if another netlist exists.

Specifying the Views and Hierarchy to Netlist

Option Description

Netlist These Views

Defines which view is netlisted for each cell or module. You use this option with the Stop Netlisting at Views.

The netlister starts at the top-level cell in the design being simulated and works down the hierarchy, selecting the appropriate view for each cell netlisted. For each cell, the netlister searches for a view from the list, in left-to-right order, and netlists the first view it finds that is on the list.

For example, if the list were behavioral verilog schematic symbol, the netlister first searches for a behavioral view, then a verilog view, and so on. If the current cell contains only a schematic and a symbol view, the netlister would netlist only the schematic view.

Generating Default Test Bench and Stimulus

Option Description

Generate Verilog Test Fixture Template

Specifies whether or not you need the netlister to generate the test fixture template.

Controlling Netlisting

Option Description

Netlist For LAI/LMSI Models

Netlister uses all Lai_verilog or lmsi_verilog cellviews for this simulation. The Lai_verilog property values indicate the use of SmartModels Library. The lmsi_verilog property values indicate the use of LM-family hardware simulation models in your analysis.

Cells that do not have the Lai_verilog or lmsi_verilog view type are netlisted according to the priorities established with the Netlist These Views and Stop Netlisting at Views options.

To attach the lai_verilog or lmsi_verilog view property to an instance on a VSE schematic, use the Edit – Properties command. The Edit – Properties command appears on the schematic window. Refer to the Virtuoso Schematic Editor L User Guide for more information about using the Edit – Properties command to attach an lai_verilog or lmsi_verilog view property.

Netlist Uppercase

Generates a netlist in all uppercase letters. This option creates compatible modules that are disparate in case.

Generate Pin Map

Instructs the netlister to create the pin mapping files necessary to convert Standard Delay Files (SDF) pin names to NC-Verilog pin names. Select this option only when you are ready to backannotate.

This option is required when the pin names for a symbol in your schematic differ from those in the Verilog library model description. After you create your pin map, your entire design is netlisted automatically to ensure that the netlister creates pin maps for the entire design.

The Generate Pin Map option must remain selected on subsequent runs. Otherwise, the netlister deletes your pin map directory.

Preserve Buses

Instructs the netlister to preserve buses (vectors) in the resulting netlist. If this option is off, the netlister expands vector nets to single-bit equivalents (scalars) in the resulting netlist. For more information on bus constructs, refer to Bus Constructs.

Netlist Switch RC

Specifies that netlisting includes user-defined RC switch properties.

Skip Null Port

Specifies that netlisting ignores floating instance ports.

Netlist Uselib

Specifies that the netlister automatically adds the 'uselib directive to the netlist when a design includes two similarly named cells from two different libraries. For detailed information, refer to Adding Directives.

Drop Port Range

Prints the module port without the port range.

Incremental Config List

Writes the renetlisted cellviews to the Configuration List.

Symbol Implicit

Suppresses printing of the net name during instance port formatting.

Assign For Alias

When enabled, specifies that the netlister uses an assignment statement for patches between nets. When disabled, specifies that the netlister applies the default cds.alias to patches between nets.

Skip Timing Information

When enabled, causes the netlister to ignore timing information assigned to instances in the design.

Netlist Explicitly

Generates name-based port lists (using connection-by-name syntax) for modules in Verilog views. Turn this option off to generate order-based port lists.This option does not apply to instances whose master module is generated by the netlister. For example, the netlister converts all schematics into Verilog modules. For instances of these modules, the netlister always creates order-based port lists.

Support Escape Names

When enabled, causes the netlister to include escaped names in the netlist.

Single Netlist File

When selected, generates a single verilog netlist instead of multiple netlists (one for each module). The netlist file is generated in the current simulation run directory with the name netlist.

Stop Netlisting at Views

Controls the level of hierarchy at which netlisting stops. After netlisting a cell, the netlister checks whether the view netlisted is on this stop list. If it is, the netlister stops expansion of the design for this cell. The order of views in the stop list is irrelevant. For example, if the stop list is functional verilog symbol, the netlister checks each netlisted cell to determine if it contains a functional, verilog, or symbol view. If it does, the netlister stops netlisting for that cell. If not, it goes on to the next cell in the design library.

Terminal SyncUp

Specifies how to synchronize terminals between an instance and its switched master. You can choose from the following three options:

  • Expand on Mismatch (default) retains the design terminals as is, unless there is a mismatch. In case of a mismatch, the netlister expands the mismatched terminals.
    Use this option to generate a pure explicit netlist with flattened buses.
  • Honor Switch Master always honors the switch master terminals.
  • Merge All merges all terminals to create simple scalar and pure bus terminals. The resulting netlist does not have any bundles or split buses.
You can also set the hnlVerilogTermSyncUp variable in the .vlogifrc file. The possible values are mergeAll, honorSM, and nil (default).

For more details, refer to Synchronizing Terminals.

Defining Global Power and Ground Signals

Option Description

Global Power Nets

Specifies the global net names you want netlisted with the supply1 wire type. Supply1 wire types are driven to logic state 1. The net names you specify must conform to global naming conventions as described in the Virtuoso Schematic Editor L.

Global Ground Nets

Specifies the global net names you want netlisted with the supply0 wire type. Supply0 wire types are driven to logic state0. The net names you specify must conform to global net naming conventions as described in the Virtuoso Schematic Editor L.

Global TimeScale Overwrite Schematic TimeScale

Specifies that the defined Global Time Scale variables (described below) overwrite any time values or units defined within a schematic. The results may vary depending on the various factors. For more information, refer to Results Dependency.

Declare Global Locally

When enabled, lets you declare global signals locally. When disabled, causes the netlister to use the default signals (Global Power Nets and Global Ground Nets).

Global Sim Time

Specifies a value for the global simulating time

Unit

Specifies the units for the global simulation time value. The valid values are s, ms, us, ns, and ps.

Global Sim Precision

Specifies a global precision value for the global simulation time

Bus Constructs

Bus constructs that cannot be represented with Verilog bus constructs are represented by using in-line concatenation, a Verilog feature. In some cases, bus names that are bundled or that are part of aliasing schemes are mapped to new names because NC-Verilog does not support certain bundling schemes. Mapped bus names are prefixed by cdsbus and have a sequence number assigned. The sequence number is a function of how many names are mapped. The following examples illustrate how bundled signals are mapped:

Adding Directives

The netlister automatically adds the 'uselib directive only when the stop view for a cell is functional or behavioral or system. When the stop view for a cell is verilog or symbol, you must add the lmoToolPath property to the library that contains the cell. Refer to the following steps for adding directives:

The lmoToolPath property is added to the specified library.

You cannot netlist two similarly named cells from two different libraries when a cell has a schematic stop view.

For more information about adding library properties, refer to the Library Manager User Guide .

Results Dependency

The results for Global TimeScale Overwrite Schematic TimeScale option vary depending on the following:

The table below describes the possible outcomes in various conditions:)

Option Enabled Option Disabled

Schematic has an assigned time scale
  • The system overwrites all assigned time scale values with the defined global time values.
  • The system converts all assigned time units to the defined global time unit scale.
  • The system does not overwrite any time scale settings within the schematic.

Schematic does not have an assigned time scale
  • The system assigns the defined global time scale values.
  • The system converts all assigned ns, ps, and fs time units to the defined global time unit scale.
  • The system appends the default time unit (1ns) to any values without time units.
  • The system does not overwrite any assigned time scale values.
  • The system converts any assigned ns, ps, and fs time units to the defined global time unit scale.
  • The system appends the default time unit (1ns) to any values without time units.

For more information on netlisting, refer to Chapter 5, “Netlisting.”

Record Signals

Specifies a set of signals to trace and save in the SHM database. The SHM database stores waveform displays. On selecting this option, the Record Signals Setup form is displayed.

The following table gives the description of the various options on the Record Signals Setup form:

Record Signals Setup Options

Option Description

Trace

Tells the system to probe a set of signals. You specify the set of signals with the cyclic button. For information on signal sets, refer to Signal Sets

In the Scope

Specifies the scope of the verilog design under simulation in which the specified object(s) is to be probed and how many scope levels to descend when searching for objects to probe if a scope is specified. You must specify one of the following arguments:

n, to descend the specified number of scopes. For example, 1 means include only the given scope, 2 means include the given scope and its subscopes, and so on. The default is 1.

All, to include all scopes in the hierarchy below the specified scope(s)

Signal Sets

The following table describes the various signal sets you can specify in the Trace option:

Signal Sets Options

Option Description

All Signals

Traces all signals in your design. This specifies that all of the declared objects within a scope, except for VHDL variables, are to be included in the probe.

All Input Ports

Specifies that all inputs within a scope are to be included in the probe.

All Output Ports

Specifies that all outputs within a scope are to be included in the probe.

All Ports

Specifies that all ports within a scope are to be included in the probe.

Only Specified Signals

Specifies that only the scopes specified are to be included in the probe.
The object(s) being traced in the All Signals, All Input Ports, All Output Ports, All Ports options apply to:

Record Signals for Batch Simulation

Signals are saved only when the simulation is run in the interactive mode. In order to save signals in Batch Mode, you should perform the following steps:

Simulation

Selecting this option displays the Simulation Setup form. This form lets you specify various options that control and affect the simulation.

The following tables describe how to complete the Simulation Setup form by specifying the options listed below:

Simulation Options

Option Description

Options File

Specifies an ASCII file containing NC-Verilog invocation command options. The file can also contain source text filenames or NC-Verilog predefined + or - options that are not available through the interface.

Suppress Warnings

Suppresses all warning messages during your NC-Verilog simulation.

Simulation Log File

Specifies the name of the file in the current run directory in which you want to store the simulation log. The default file is simout.tmp.

Reference Libraries

Option Description

Files

Identifies vendor-supplied Verilog ASIC libraries. NC-Verilog also scans this file for module and UDP definitions that have not been resolved in the normal source text files specified on the command line. This option takes any valid operating system file for an argument.

Directories

Specifies the path (or paths) to library files that contain module and UDP definitions. NC-Verilog searches these directories when it compiles your netlist and functional views.

Other Options

Specifies the extensions, such as .v, of files that you want to refer to in the specified directories while simulating a design.

Pack Reference Libraries to Reduce Start-up Time

This option is enabled once you specify a reference library name. You can use this option to specify a file path in which the reference library files/directories will be compiled. A packed reference library reduces the simulator start-up time significantly and it is useful for those reference libraries that are large in size and are changed rarely.

On recompilation, a packed library needs to be unpacked, compiled, elaborated and repacked. This is required only if the library files/directories have been modified. You can confirm the unpacking and repacking of reference library by using the Repacking Library dialog box.

Debug Options

Option Description

Optimize for Best Performance

Sets the visibility access for all objects in the design. This is used to increase the simulation performance by not giving read, write or connectivity access to the simulation objects. By default this button is disabled.

Object Access

Specifies the read, write and connectivity access of the simulation object. The default value is read only access. For information, refer to Object Access Options

Enable Line Debugging

It set to use line breakpoints and single stepping. If this option is not set, line breakpoints and single stepping would still not be available even when you select read, write and connectivity access.

Delay Options

Option Description

Mode

Globally alters the delay values specified in your design. You can filter results by setting the following options:

Zero ignores all module path delays, timing checks, and structural and continuous assignment delays.

Path uses delay information from specified blocks that contain module path delays. It ignores structural and continuous assignment delays with the exception of trireg charge decay times.

Unit ignores module path delays and timing checks and converts all structural and continuous assignment delays that are nonzero to one time unit.

Distributed uses the delay on nets, primitives, and continuous assignments. It ignores module path delays.

None uses all of the delays in your netlist.

Type

Specifies the delay type. You can filter results by setting the following options:

Minimum selects all minimum delays.

Typical selects all typical delays.

Maximum selects all maximum delays.

SDF Command File

Specifies the name of the SDF command file that you need ncelab to annotate. If an SDF delay file already exists, then the system automatically generates an SDF command file and populates the filename into this field.

Object Access Options

The following table describes the access rights for the Object Access option:

Object Access Options

Option Description

Read

It is used if you need to probe objects in the design and generate an SHM or VCD database. This lets you use SimVision or Signalscan to view waveforms or SimCompare to compare databases.

Write

It is used if you need to specify values using the interactive simulation interface. For example when you use the force or deposit commands from the interactive simulation interface.

Connectivity

It is used to if you need to display the load or driver information. For example, this information is required by the driver command and by the Signal Flow Browser.

Pulse Control Options

Option Description

Error%

Sets the error limit to one of the three values: 0, 50, or
100 percent. The default setting for NC-Verilog is 100.

A pulse that is less than or equal to this specified percentage, but greater than the reject limit, sets the module path output pulse to the e logic value.

Reject%

Sets the reject limit to one of three values: 0, 50, or 100 percent. The default setting for NC-Verilog is 100.

Use Pulse Control Parameters

Enables you to use PATHPULSE$ special parameters to override the global pulse control.

Timing Options
Option Description

Enable Timing Check

It is set to use the two timing check options which are disabled by default.

Allow Negative Values

It is set to allow negative values in $setuphold and $recrem timing checks in the Verilog description and in SETUPHOLD and RECREM timing checks in the SDF annotation. If this option is not set, any negative values in the Verilog description or in the SDF annotation are set to 0 and a warning is generated.

Ignore Notifiers

It is set to ignore notifiers in timing checks.

Simulation Compare

Selecting this option displays the Simulation Comparison Setup form.

The following tables describe the various form options:

File Options

Option Description

Rule File

Specifies the name of comparison rule file. You can also specify an option for the system to create a comparison rule file by reading the entries in the form. Alternatively, you can supply your own rule file in which case, the system reads into your rule file to drive the simulation comparison.

Golden Database File

Specifies the golden file to be used for comparison

Compare Database File

Describes the contents of the current director. The current directory contains the comparison SHM database results, which you compare to the golden database results described in the previous option.

Comparison Configuration Options

Option Description

Specify Time Range of Interest

On selection, enables you to specify the time range that contains the signal events that you want to compare. Use absolute time values to define the range. For more information on its options, refer to Timing Options

Perform Clock Edge Sample Comparison

On selection, enables you to perform a clock edge sample comparison. For more information on its options, refer to Clock Edge Sampling Options

Max. Mismatches

When enabled (default), requires you to enter a number in the associated text field that specifies the number of mismatches that you want the system to find. The system stops the comparison when the specified limit is reached. When disabled, the system ignores the associated text field and continues the comparison regardless of the number of mismatches found.

Timing Options

Option Description

Start Time

Specifies when the simulation comparison begins.

Finish Time

Specifies when the simulation comparison ends.

Time Unit

Displays the units of measure for the time range. You cannot modify this value.

Positive Tolerance

Specifies the positive tolerance for a matching event. This is the time window after a golden event during which a test event may match.

Negative Tolerance

Specifies the negative tolerance for a matching event. This is the time window after a golden event during which a test event may match.

Time Unit

Displays the units of measure for the Cycle Time, Strobe Offset, and Strobe Width fields. You cannot modify this value.

Clock Edge Sampling Options

Option Description

Clock Signal to Use

Specifies the clock signal to be used in the design

Sample Time Unit Offset

Specifies the number of time units by which the sampling times for the comparison and the relative times at which setup and hold timing checks occur are offset from the edge of the clock signal. The default value is 0. This means that each sample is taken at the clock edge and all setup and hold checks are performed relative to the clock edge.

Clock Setup Time

Specifies the setup time for the clock signal used.

Clock Hold Time

Specifies the hold time for the clock signal used.

Time Unit

Displays the units of measure for the Cycle Time, Strobe Offset, and Strobe Width fields. You cannot modify this value.

Active Clock Edge for Sampling

Specifies the active edge of the clock signal at which sampling occurs. It can be positive, negative or both.

Display Results In Options

These options let you manage the display of comparison results. When there are mismatches, you can specify that the software display the results in either an STV window or a SignalScan window, or both. When there are no mismatches, neither window appears. The following table describes the various options:

Option Description

Text File

Specifies that you want the software to store the comparison results in the text file displayed in the text field.

From Incisive Unified Simulator 82 (IUS82), the default name of the text file is compare.out. For previous IUS versions, the default name is compareScan.out.

When you enable this option (default), the software automatically opens the file in an STV (Source Text Viewing) window after completing the comparison. However, the software does not open the file if there is a mismatch in the simulation results.

Report Verbosity Level

Specifies the level of detail for the text file. You can choose the following from the drop down list:

  • Summary - summarizes the mismatch information
  • Detailed - writes a detailed report for each mismatch

Waveform Viewer

Specifies that you want the software to store the comparison results in a waveform database.

When enabled (default), the software automatically opens a SimVision or Signalscan window that displays the waveforms after completing the comparison. However, the software does not display the waveforms if there is a mismatch in the simulation results.

Difference Database

Specifies the waveform database where the software stores the comparison results.

Path to Database

Specifies the path to the directory where the difference database resides.

Cross Selection Setup

Selecting this option displays the Cross Selection Setup form.

The following table describes the various form options:

Cross Selection Options

Option Description

Cross Selection from Schematic Editor to SimVision

On selection, enables you to select an object in the schematic design in Virtuoso Schematic Editor and have the corresponding simulation object selected in SimControl.

Cross Selection from SimVision to Schematic Editor

On selection, enables you to select a simulation object in SimControl and have the corresponding object selected in the schematic design in Virtuoso Schematic Editor.

Results Menu

Netlist

Displays the netlist or a map file in a view window. The netlist file contains the Verilog text description of your design. A map file describes how the system maps names between Cadence® Verilog and the Design Framework II environment. When you netlist your design, the netlister generates a netlist and a map file. This command opens the View Netlist Run Files form that you use to specify the type of file and the name of the file you want to view.

If the View Netlist Run Files form is blank or does not display all the libraries you want to see, click Load.

The following table describes the various form options:

View Netlist Run Options

Option Description

View File

Specifies which type of file that you want to view. You can select one of the following:

Map specifies that you want to view a map file.

Netlist (default) specifies that you want to view a netlist file.

The netlist or a map files are displayed in a view window. For more information about a view window, see “View Windows”

File Path

Displays the full path to the library and cellview you select from the list boxes. You cannot edit this field.

Library Name

Displays the design library you select from the list box below this field. You cannot edit this field.

Cell Name

Displays the cell you select from the list box below this field. You cannot edit this field.

Job Monitor

Displays the Analysis Job Monitor window, which you can use to select options that control batch jobs or to view information about batch jobs.

Analysis Job Monitor Window

On selecting Job Monitor option, the Analysis Job Monitor window appears. The window displays the following:

The Analysis Job Monitor form lists all batch simulations started during the current session.

Using Job Monitor

The option buttons at the top of the window let you control batch simulations. To apply an option to a batch job, click the job selection button for a batch job and then click an option button.

Help Menu

The Help menu lets you access help on using NC-Verilog Integration Environment. You can also access online support and resources from this menu.

Fixed Menu

This section describes each fixed menu command. Until you start an interactive simulation, Start Interactive is the only fixed menu command you can access.

Initialize Design

starts the NC-Verilog simulator. You must initialize design before you can access the other fixed menu commands.

Generate Netlist

triggers the OSS netlist() routine to generate an incremental hierarchical netlist in the specified run directory.

Simulate

simulates the design in either interactive or batch mode.

Simulation Compare

invokes the SimCompare tool to compare the golden and test SST2 databases.

Customizing Command Form Options

The default option settings for the NC-Verilog forms are set by the system when you enter an empty run directory. The initial settings are supplied with the software. When you edit the default settings on a form, the system saves the new settings to the .vlogifrc file. The .vlogifrc file settings override the default setup options supplied with the NC-Verilog software or supplied by a user in an .simrc file.

The .vlogifrc file is rewritten whenever you complete one of the following actions:

Forms that you can customize

In general, you can customize some of the options for each of the following forms:

For more information, refer to Appendix A, “Customizing Your Environment”.


Return to top
 ⠀
X