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Running the Simulation

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This chapter includes the following:

• Simulation Process Flowchart
• Introduction
• Setting SDF Delay Annotation
• Setting Simulation Setup Options
• Simulating a Design
• Cross-Selecting Design Objects
• Running a Batch Simulation
• Comparing Simulation Results

Simulation Process Flowchart

Introduction

In NC-Verilog Environment, you can run two types of simulation, namely:

• Interactive
• Batch

In Interactive simulation you can select the steps to Compile, Elaborate and, Simulate. After the design is successfully compiled and elaborated, the SimVision user interface opens. You can use this interface interactively to simulate and debug the design.

When you run a batch simulation, the Compile, Elaborate and, Simulate are run one after the other and do not require any user intervention.

Before you run a simulation, you must set the SDF delay annotation options and the simulation setup options.

Setting SDF Delay Annotation

In the NC-Verilog Integration Environment, you can annotate delays into your design either before you start simulation. This section describes how to read in a delay file at simulation time zero. The term time zero refers to the time before you start interactive or batch simulations.

Virtuoso Schematic Editor recognizes delay files written in SDF (Standard Delay Format). You can use SDF to create either a delay file for backannotation or a constraints file for forward annotation.

You set the SDF delay annotation using the SDF Delay Annotation Setup form. This form is accessed from the Commands menu. Once you specify the various options in the SDF Delay Annotation Setup form, the information you enter in the form is saved in the run directory and is applied each time you run a simulation.

Setting the Delay Annotation Options

This table shows you how to fill in the delay annotations on the Setup Environment form.

How Delay Annotation Options Affect Simulation

Option	Description
Suppress SDF CellType Checking	Turn this on to suppress the CellType mismatch checking performed by NC-Verilog SDF backannotator.
Suppress sdf2sdf3 Running	Turn this on to suppress the running of the sdf2sdf3 process when you start a simulation. When this option is on, the simulator reads the sdf2sdf3 information from the last simulation.
Suppress sdf2sdf3 Warning Message	Turn this on to suppress the warning messages generated by sdf2sdf3.
Delay File	Type in the path to your SDF delay file. If the file is in the run directory, you need only enter the file name.
sdf2sdf File	Type in the name of a file to store information generated by the sdf2sdf process. When you suppress the sdf2sdf process, the simulator reads information from the file specified in this field.
SDF Scope	Type in the name of the scope you want the system to preappend to the sdf2sdf file.
SDF Module Instance	Type in the name of the module that the SDF file annotates.
Delay Config File	Type in the name of your annotator configuration file, if you have one. Refer to the SDF Annotator User Guide for more information.
Log File	You can change the default log file name, which is sdf.log.
Use Delay Type	Select a delay type. This value overrides the type specified in the configuration file. If you select Tool Control, the software bases the delay type on the delay mode you enter on the Simulation Options form.
Scale source Delay	Select the type of delays from the delay file against which the scaling factor is applied. Your selection overrides the configuration file value (if any) unless you select From Config.
Scale Factor	Enter the scale factor to apply to the delays you selected in Scale Source Delay. Leave these fields set to 1 (the default value) if your delay file contains computed delay values. The SDF annotator uses these values to scale the minimum, typical, and maximum timing data from the SDF file before they are backannotated to NC-Verilog Integration. You must enter positive real numbers in the Minimum, Typical, and Maximum fields, for example, 0.5, 1.0, and 1.6.

Setting Simulation Setup Options

You use the Simulation Options form to set options that control simulation. These options let you control acceleration, delays, and pulses. The form also lets you specify the Verilog libraries and the executable that you want to use.

You set the simulation options using the Simulation Setup form. This form is accessed from the Commands menu. Once you specify the various options in the form, NC-Verilog Integration sets up the simulation according to the options that you have specified.

The following tables describe how to complete the Simulation Options form by specifying the options.

Options File

Option	Description
Options File	Type in a path to an options file relative to the directory from which you invoked the Command Interpreter Window (CIW). The simulation run is based on the Verilog options in the file.

Reference Libraries Options

Option	Description
Library Files	Type in the paths to the library files containing third-party Verilog libraries used with this design.
Library Directories	Type in the paths to the dedicated library directories containing third-party Verilog libraries used with this design.
Pack Reference Libraries to reduce Start-up Time	Turn this option on to specify a file path in which the reference library files/directories will be compiled.

Debug Options

Option	Description
Optimize for Best Performance	Turn these options on to set the visibility access for all objects in the design. Object Access specifies the read, write and connectivity access of the simulation object. The default value is read only access.
Enable Line Debugging	Turn this option on to use line breakpoints and single stepping.7

Delay Options

Option	Description
Zero	Turn this option on if you do not want to apply delays.
Path	Turn this option on to use path (pin-to-pin) delays for objects that have both path and distributed delays attached to them.
Unit	Turn this on to apply one delay unit per gate.
Distributed	Turn this on to use distributed delays for objects that have both path and distributed delays attached to them.
None	Turn this on if you do not want to use all of the delays in your netlist.
Types	Specify a delay value to apply during simulation: minimum, typical, or maximum.
SDF Command File	Type in the paths to the SDF command file that you need ncelab to annotate.

Pulse Control Options

Option	Description
Error	Type in a percentage. The unknown value is assigned to the output pulse for any input pulse that is both shorter than or equal to this percentage of the module path delay, and greater than the reject percentage.
Reject	Type in a percentage. Input pulses that are shorter than this percentage of the module path delay are ignored.
Use PulseControl Parameters	Turn this option on to read in the PATHPULSE$ spec param from the Verilog model in the Verilog library, which overrides the error and pulse settings. (Verilog +pathpulse option)

Timing Options

Option	Description
Enable Timing Check	Turn this option on to specify the various types of timing checks.

Message Control Options

Option	Description
Suppress Warnings	Turn this option on to suppress warnings. For example, turn this button on if you do not want to be slowed down by warnings displays during a large simulation.

Simulating a Design

To simulate a design, you use the Simulate command in the Fixed menu. Alternatively you can also use the Simulate command from the Commands menu.

In interactive simulation, you select the option to compile, elaborate and simulate the design from the main NC-Verilog window. When you select all the three options, the system invokes SimVision’s Design Browser and the Console windows after it successfully compiles and elaborates the design.

In the Design Browser window, you can interactively simulate and debug the design. Using the Design Browser window, you can directly interact with the simulator to open a database, trace signals, single step, set breakpoints, observe signals, and perform many other functions to verify your design. The Design Browser is part of the Cadence SimVision Analysis environment which is a unified graphical debug environment for Cadence simulators. For more information on the SimVision user interface, refer to the Cadence SimVision Analysis Environment User Guide.

In interactive simulation, you can cross-select design objects between SimVision tools and Virtuoso Schematic Editor. For details, see “Cross-Selecting Objects during Interactive Simulation”.

If you want to view the simulation results output in the SimVision window, then the SKILL variable simNCVerilogNostdout should be set to nil in the CIW or .simrc before running the simulation. The default value of this variable is t.

Cross-Selecting Design Objects

You can cross-select the objects of a design between Virtuoso Schematic Editor and the SimVision tools. Cross-selecting objects helps you identify a specific object in the schematic design corresponding to the object in SimVision, and vice versa.

You can cross-select objects when you perform interactive simulation. You can also use the available simulation data of a design and cross-select the design objects. The simulation data can be generated using the NC-Verilog Integration Environment or a standalone Verilog simulator. You can also cross-select iterated instances.

The following figure illustrates how you can cross-select an object.

Cross-Selecting an Object

This section includes the following topics:

• Cross-Selecting Objects during Interactive Simulation
• Cross-Selecting Objects Using Simulation Data.
• Cross-Selecting Iterated Instances

Cross-Selecting Objects during Interactive Simulation

You can cross-select the objects of a design between SimVision tools and Virtuoso Schematic Editor when you perform interactive simulation. For information on interactive simulation, see “Introduction” and “Simulating a Design”.

To cross-select objects during interactive simulation:

1. Choose Setup — Cross Selection from the main NC-Verilog window. The Cross Selection Setup form appears.
   
   
2. Select Cross Selection from Schematic Editor to SimVision to be able to select an object in the schematic design and have the corresponding simulation object selected in the SimVision user interface.
3. Select Cross Selection from SimVision to Schematic Editor to be able to select a simulation object in SimVision and have the corresponding object selected in the schematic design.
4. Click OK.

When SimVision is launched for interactive simulation, you can cross-select objects depending on the cross-selection setup. You can cross-select objects between Virtuoso Schematic Editor and SimVision tools, including SimVision Design Browser, SimVision Waveform, and SimVision Tracer. See the figure Cross-Selecting an Object.

Cross-Selecting Objects Using Simulation Data

You can cross-select the objects of a design between SimVision tools and Virtuoso Schematic Editor using the available simulation data to perform post-simulation analysis. The simulation data can be generated by the NC-Verilog Integration Environment or a standalone Verilog simulator. For example, you can generate the Verilog netlist of a design using the NC-Verilog Integration Environment. You can then use this netlist to simulate the design using the irun tool from the command line. The results of this simulation can be used to cross-select design objects between SimVision tools and Virtuoso Schematic Editor.

The executable and log file names will depend on the simulator being used. For the changes in the executable and log file name when using the Xcelium simulator, see Running Simulations with Xcelium.

To specify the simulation data for cross-selecting design objects:

1. Choose Commands — Post Simulation Analysis from the main NC-Verilog window. The Post Simulation Analysis form appears.
   
   
2. Specify the following information in the form. You can click the browse button next to a field to select the input data:
   

   Field	Description
   Netlist Run Directory	Select this option if you want to specify the run directory. Then specify the path of the run directory.
   Cell View	Select this option if you want to specify the top-level design cellview instead of the run directory. Then specify the library, cell, and view.
   Simulation Directory	Specify the path of the simulation database.
   SimVision Database	Specify the path and filename of the SimVision database .trn file.
   Hierarchy Prefix	This field includes the hierarchy prefix used in the testbench, such as test.top or test:top. You can use a period (.) or a colon (:) as the delimiter in the hierarchy prefix.
   Additional Arguments	This field lets you specify additional arguments that must be passed on to xrun. You must specify the arguments as follows:   -snapshot incr -xmlibdirname ./incrsnap

3. Click OK.
   The specified SimVision database opens in SimVision Design Browser and you can cross-select objects.
   
   When you initiate the cross-selecting functionality for post-simulation analysis, the cross-selection options in the Cross Selection Setup form are selected automatically.

To cross-select an object, select it in SimVision Design Browser. The schematic with the corresponding object gets highlighted in Virtuoso Schematic Editor. You can cross-select objects between Virtuoso Schematic Editor and SimVision tools, including SimVision Design Browser, SimVision Waveform, and SimVision Tracer. See the figure Cross-Selecting an Object.

Cross-Selecting Iterated Instances

You can cross-select the iterated instances in a design during interactive simulation or post-simulation analysis.

To enable cross-selection of iterated instances:

1. Ensure that the iterated instances are printed in the expanded form in the netlist in the format baseName_bit_, such as I0_0_.
   For this, set the flag vlogExpandIteratedInst to t in Virtuoso CIW or in .simrc before netlisting the design.
2. Set the flag to enable cross-selection of iterated instances vlogProbeExpandedIterInst to t in Virtuoso CIW or in .simrc.

For cross-selection, the expanded names of the iterated instances in the netlist are mapped to their corresponding instances in the schematic. For example, the expanded iterated instance I1_0_ in the netlist is mapped to I1<0> in the schematic. When you select I1_0_ in SimVision, the corresponding instance I1<0> is selected in Virtuoso Schematic Editor automatically.

The following figure illustrates the iterated instance I1<0:1> in the schematic view and its corresponding netlist, where the iterated instances are printed in the expanded form as I1_0_ and I1_1_. The figure also shows cross-selection of the iterated instance.

Notes:

• To avoid conflicts during cross-selection of iterated instances, ensure that the scalar instances in the schematic are not named in the format baseName_digits_, such as I0_0_. Moreover, the schematic should not have illegal Verilog names that require mapping to other legal Verilog names.
• If an iterated instance is selected in the schematic, its corresponding scalar instance in SimVision is not selected automatically because of ambiguity in the names.

For more information on iterated instances, see “Iterated Instances Support”.

Running a Batch Simulation

Running a batch simulation results in the execution of all the three options: Compile, Elaborate and Simulate in one go.

You can start batch simulation by selecting the Batch option in the main NC-Verilog window. The batch option is part of the Simulate Options in the main NC-Verilog window.

When a batch simulation finishes processing, a dialog box appears. The dialog box informs you that the batch job in the specified run directory completed successfully.

Monitoring Batch Simulations

The NC-Verilog Integration Environment lets you suspend batch jobs temporarily so that no processing time is allocated to the job. You can continue a suspended batch simulation whenever you choose.

To suspend or continue a batch simulation, you use the commands and options available on the Analysis Job Monitor form.

You can also change the priority of a batch job so that more or less processing time is allocated to the job.

To open the Job Monitor form, you select the Job Monitor command from the Results Menu in the main NC-Verilog window. The Analysis Job Monitor form appears.

The Analysis Job Monitor form displays the status for each batch job currently running or which has run during the current Schematic Editor session.

For more information on Job Monitor, see Job Monitor.

Comparing Simulation Results

SimCompare is used to compare the results obtained from different simulations. It provides a text description of any differences found.

Before using the tool, you need to set the simulation comparison options in the Simulation Comparison Setup form. This form can be accessed by selecting the Simulation Compare command from the Setup Menu in the main NC-Verilog window. For more information on the Simulation Comparison Setup form, refer to Simulation Compare.

To start the comparison of simulation result, select the Simulation Compare command from the Fixed Menu. Alternatively you can also select the Simulation Compare command from the Commands menu. On selection of Simulation Compare command, SimCompare is launched in the background. For more information on using the SimCompare tool, refer to the SimCompare User Guide.

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