Product Documentation
Spectre Circuit Simulator Components and Device Models Reference
Product Version 23.1, June 2023

Model Overview

UTSOI2 has been developed with the aim to describe device operations with a strongly inverted back interface. Therefore, an original analytical procedure has been developed to calculate the exact values of the surface potentials at front and back interfaces in all operating conditions. Besides this surface potential calculation, new drain current and intrinsic charge models have also been developed. Not that the new model core is valid not only for FDSOI technologies, but also for all Independent Double Gate device architectures.

In UTSOI2, the effect of backplane depletion, computed through a bulk MOSFET like surface potential calculation has been introduced. This effect can be activated through the value of the SWSUBDEP flag. If the flag is set to 0, the backplane is assumed metallic, as in UTSOI1.

UTSOI2 offers the possibility to define two different junctions at source and drain sides, as done in PSP. Junction related parameters are therefore duplicated, the drain related parameters having the same name as their source side counterparts plus a final “D”. This possible junction asymmetry can be activated using the SWJUNASYM flag. When it is de-activated, drain related parameters are ignored.

Starting with version 2.1.0, the temperature node of the transistor (Tnode), that gives channel temperature elevation induced by self-heating, is accessible from the circuit netlist (that is, declared as inout). Therefore, from version 2.1.0, transistor instantiation accepts five nodes: drain, gate, source, bulk, and internal temperature.

Model Structure

The model structure of utsoi2 model is the same as different versions of utsoi1 and similar to PSP3 and PSP4. It is based on the hierarchical construction featuring two levels of parameter set:


Return to top
 ⠀
X