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UTSOI2 Model

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UTSOI2 is the second version of the UTSOI model, compact model dedicated to Fully-Depleted on Silicon-On-Insulator (FDSOI) technologies with low-doped channel, developed at CEA-LETI. The device architecture described by this model is shown in the figure below.

This chapter contains the following information about the UTSOI2 model:

• Model Overview
  • Model Structure
• Version Update and Enhancement
• Geometrical dependences, stress effects and junction asymmetry
• Scaling Equations
• Stress Model
• Asymmetric Junctions
• Model Equations
  • Internal Parameters Including Temperature Dependencies
  • Terminal Voltage Conditioning
  • Backplane Depletion
  • Channel Current
  • Gate Current, Intrinsic Charges and Overlap Related Variables
  • Gate Current
  • Gate Induced Drain/Source Leakage (GIDL/GISL)
  • Charge Model
  • Self-Heating
  • Noise Model
  • Total Current and Charges
• Operating Point Output
• Component Statements

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