Product Documentation
Cadence Verilog-AMS Language Reference
Product Version 22.09, April 2022

E


Unsupported Elements of Verilog-AMS

The Cadence® Verilog®-AMS language is specified in the Verilog-AMS Language Reference Manual: Analog & Mixed-Signal Extensions to Verilog HDL, produced by Open Verilog International. The Cadence implementation of Verilog-AMS does not support all of the specified elements of the Verilog-AMS language in all the contexts in which the language specification says they are to be supported.

The tables in this section list the unsupported elements according to the following classifications:

Unsupported Elements for Behavioral Contexts

Feature Comment

Net attributes, except for net.potential.abstol and net.flow.abstol, which are supported

String variables

Cannot be assigned in analog block. Cannot be used in $strobe in the analog block.

Using probes containing vector net elements in a digital block.

Out-of-module references

Not supported to analog nets, branches, or nature attributes.

Standard math and transcendental functions

Inside the analog block, expressions that contain hierarchical references are not supported. Domain ranges are checked only for exp, sqrt, pow, and atan2.

$rdist functions

Supported in analog contexts but not in digital contexts.

Global events

The @analog_identifier form is not supported.

@timer

Not supported in the digital context.

$realtime

Not supported in the analog context. Use $abstime instead, in the analog context.

Unsupported Elements for Behavioral Analog Contexts

Feature Comment

Parameters used to specify ranges for the generate statement

Parameter declarations

Not supported in analog user-defined functions.

The genvar statement

Arrays passed to functions

ddt (time derivative) operator

Nesting is not allowed. For example, ddt(ddt()) is prohibited. The abstol argument has no effect. A nature cannot be used as an argument.

Laplace transform filters

Parameter-sized array arguments are not supported.

Analog functions

Parameters are not allowed as arguments.

Analog vector nets

Not supported for the Tcl value command.

Digital transition sensitivities

Transition sensitivities such as @dVal are not supported in analog contexts. Event sensitivities such as

@(posedge dVal or negedge dVal)

must be used instead.

The concatenation operator

$stime

$time

$monitor and $fmonitor

$monitor off/on

$printtimescale

$timeformat

$bitstoreal

$itor

$realtobits

$rtoi

$readmen used with the %b, %h, and %r specifications.

Unsupported Elements for Structural Contexts

Feature Comment

Derived natures

Overriding nature attributes from disciplines

Array ranges for nets

Array ranges for ground nodes

Parameter arrays

Parameter array declarations are not supported. Parameter array assignments are supported only in analog primitives.

Module instantiation inside a generate block

Generate blocks, because they can be used only in analog blocks, can contain only behavioral code.

Parameter-sized vector nets

User-defined attributes

Only the Cadence huge, blowup, and maxdelta attributes are supported.

Vector branches

Vector arguments for simulator functions

Vector ground nodes

Parameter-sized ports

Out-of-module references

Supported for voltage probes on nets. Not supported for branches, or for nature attributes.

Discipline resolution

If out-of-module references are used in port connections, the port discipline is not used to determine the discipline of the out-of-module reference.

net_resolution

Nodesets on continuous nets

The next list contains only VPI functions. The unsupported aspect of these functions is that they cannot be called with wreal arguments, digital real vectors, or analog arguments of any kind.

Unsupported Elements for Behavioral Digital Contexts When wreal Arguments Are Used

Feature Comment

@timer

$compare

$strobe_compare

$countdrivers

$deposit

$incpattern_read

$async$and$array

$async$nand$array

$async$or$array

$async$nor$array

$sync$and$array

$sync$nand$array

$sync$or$array

$sync$nor$array

$async$and$plane

$async$nand$plane

$async$or$plane

$async$nor$plane

$sync$and$plane

$sync$nand$plane

$sync$or$plane

$sync$nor$plane

$q_initialize

$q_full

$q_remove

$q_add

$q_exam

$scope

$dumpports

$dumpports_close

$lsi_dumpports

$lsi_close

$writememb

$writememh

$recordvars

$recordfile

$recordon

$recordoff

$signalscan

$signalscankill

$signalscanabort

$recordabort

$recordclose

$recordfilecopy

$recordfilechange

$signalscanconnect

$signalscancommand

$recordsetup

The Cadence Verilog®-AMS language is specified in Annex C of the Verilog-AMS Language Reference Manual: Analog & Mixed-Signal Extensions to Verilog HDL, produced by Open Verilog International. The Cadence implementation of Verilog-AMS does not support all of the specified elements of the Verilog-AMS language in all the contexts in which the language specification says they are to be supported.

The tables in this section list the unsupported elements according to the following classifications:

Unsupported Elements for Behavioral Contexts

Feature Comment

Hierarchical names, except for node.potential.abstol and node.flow.abstol, which are supported

Using 1’b1 constant specification

String variables

Cannot be assigned in analog block. Cannot be used in $strobe in the analog block.

Using probes containing vector net elements in a digital block.

String variables

The %b and %B format characters

The \ddd octal specification of a character

The concatenation operator

Enforcement of input, output, and inout

Out-of-module references

Not supported to analog nets, branches, or nature attributes.

Case equality (=== and !==) operators

casex and casez statements

Standard math and transcendental functions

Outside the analog block, arguments to functions must be constant expressions. Inside the analog block, expressions that contain hierarchical references are not supported. Domain ranges are checked only for exp, sqrt, pow, and atan2.

$rdist functions

Global events

The @analog_identifier form is not supported.

@timer

Not supported in the digital context.

Driver access functions

Driver_update is not supported.

$realtime

Not supported in the analog context. In that context, use $abstime instead.

$stime

$time

$monitor and $fmonitor

The %b, %o, and %h specifications for $display, $fdisplay, $write, $fwrite, $monitor, $fmonitor, $strobe, and $fstrobe

$monitor off/on

$printtimescale

$timeformat

$bitstoreal

$itor

$realtobits

$rtoi

$readmen used with the %b, %h, and %r specifications.

$random

The seed must be an integer constant expression, not an unsigned integer.

Unsupported Elements for Behavioral Analog Contexts

Feature Comment

Parameters used to specify ranges for the generate statement

Parameter declarations

Not supported in analog user-defined functions.

The genvar statement

Arrays passed to functions

Accessing X and Z bits of a discrete net from a continuous context.

ddt (time derivative) operator

Nesting is not allowed. For example, ddt(ddt()) is prohibited. The abstol argument has no effect. A nature cannot be used as an argument.

idt (time integral) operator

The abstol argument has no effect. A nature cannot be used as an argument.

idtmod (circular integrator) operator

The abstol argument has no effect. A nature cannot be used as an argument.

Transition filter

The time_tol argument is not supported.

Laplace transform filters

Parameter-sized array arguments are not supported.

Analog functions

Parameters are not allowed as arguments.

‘default_transition directive

analog vector nets

Not supported for the Tcl value command.

Unsupported Elements for Structural Contexts

Feature Comment

Ordered parameter lists in hierarchical instantiation

Not supported for analog primitives.

Named nodes in hierarchical instantiation

Connecting the ports of instantiated analog primitives to digital wires

Derived natures

Overriding nature attributes from disciplines

Array ranges for nets

Array ranges for ground nodes

Parameter arrays

Parameter array declarations are not supported. Parameter array assignments are supported only in analog primitives.

Parameter-sized vector nets

The defparam statement

The ground declaration

User-defined attributes

Only the Cadence huge, blowup, and maxdelta attributes are supported.

Vector branches

Vector arguments for simulator functions

Vector ground nodes

Parameter-sized ports

Out-of-module references

Not supported to analog nets, branches, or nature attributes.

Discipline resolution

If out-of-module references are used in port connections, the port discipline is not used to determine the discipline of the out-of-module reference.

net_resolution

Many of the items in the next list are VPI functions. The unsupported aspect of these functions is that they cannot be called with wreal arguments, digital real vectors, or analog arguments of any kind.

Unsupported Elements for Behavioral Digital Contexts

Feature Comment

Analog transition sensitivity

Not supported in digital contexts.

$compare

$strobe_compare

$countdrivers

$deposit

$incpattern_read

$async$and$array

$async$nand$array

$async$or$array

$async$nor$array

$sync$and$array

$sync$nand$array

$sync$or$array

$sync$nor$array

$async$and$plane

$async$nand$plane

$async$or$plane

$async$nor$plane

$sync$and$plane

$sync$nand$plane

$sync$or$plane

$sync$nor$plane

$q_initialize

$q_full

$q_remove

$q_add

$q_exam

$scope

$dumpports

$dumpports_close

$lsi_dumpports

$lsi_close

$writememb

$writememh

$recordvars

$recordfile

$recordon

$recordoff

$signalscan

$signalscankill

$signalscanabort

$recordabort

$recordclose

$recordfilecopy

$recordfilechange

$signalscanconnect

$signalscancommand

$recordsetup

The items in the next list are deprecated features. The Cadence implementation of Verilog-AMS supports these features, but might not in the future. These features are no longer supported in the standard specification of the language.

Deprecated features

Deprecated feature To comply with the current standard,...

$dist_ functions in the analog block

Consider using the $rdist functions.

generate statement in the analog block

Use the genvar statement.

The second argument of the cross operator being a non-integer type

Change the second operator to an integer type.

Using for, while and repeat loop statements for the timer function

Use a genvar loop for the timer function.

Unassigned variables

Assign each variable. Unassigned variables are considered digital variables.

generate

Use a genvar loop instead.

The second argument of the last_crossing operator being a non-integer type

Change the second operator to an integer type.

The items in the next list are Cadence extensions. These features are not part of the standard specification of the language.

Cadence extensions

Feature

Cadence syntax for attributes

mfactor attribute

dynamicparams

$cds_iprobe

Inherited parameters


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