Glossary
A
Abbreviation for Analog-to-Digital Converter.
A circuit that converts analog signals to discrete states or levels. The output numbers are usually power of two sent to a digital bus.
A wave that can be heard by humans; frequency is in the range of 20-20,000 hertz.
The context of statements that appear in the body of an analog block in a mixed-signal (analog-digital) model such as Verilog-AMS. Anything evaluated by the analog simulator, such as an analog simultaneous statement, in the VHDL-AMS model.
An analog hardware description language for describing analog circuits and functions.
A port whose connections are both analog.
A hierarchical collection of interconnected nets, where all the nets are of a continuous discipline.
B
The mathematical mapping of inputs to outputs for a module, including intermediate variables and control flow.
A version of a module with a unique set of parameters designed to model a specific component.
A level within the behavioral description of a module, delimited by begin and end.
A path between two nodes. Each branch has two associated quantities, a potential and a flow, with a reference direction for each.
C
Abbreviation for Component Description Formats.
Properties attached to a library element or cell view. Cadence® Virtuoso® Analog Design Environment netlister uses CDF properties to dump the element instantiation in the simulation netlist.
The fundamental unit within a system. A component encapsulates behavior and structure. Modules and models can represent a single component, or a component with many subcomponents.
A module automatically or manually inserted by using the connect statement, which contains the code required to translate and propagate signals between the analog and digital nets comprising a signal.
The expressions and statements that relate the outputs, inputs, and parameters of a module. These relationships constitute a behavioral description.
Same as analog context—the context of statements that appear in the body of an analog block in a mixed-signal (analog-digital) model such as Verilog-AMS. Anything evaluated by the analog simulator, such as an analog simultaneous statement, in the VHDL-AMS model.
A net of a continuous discipline.
A variable whose value is calculated in the continuous domain.
The conditional and iterative statements that control the behavior of a module. These statements evaluate variables (counters, flags, and tokens) to control the operation of different sections of a behavioral description.
A module instantiated inside the behavioral description of another, “parent” module.
D
Abbreviation for digital-to-analog converter.
A device that accepts a digital input and produces an analog output. For example, an 8-bit DAC would convert an input of 8 binary signals into a single analog (real) value.
The former Cadence Design Framework II, which has now become Virtuoso Design Environment in IC 6.1.
Abbreviation for Differential Nonlinearity.
Classical static measurement for the ADC circuit that shows the difference between the ideal and measured ADC step width in least significant bit (LSB) units. The ADC DNL goal is to stay within ± 0.5 LSB.
A definition of the properties of a variable, node, port, parameter, or net.
The context of statements that appear in a location other than an analog block.
The set of drivers and receivers interconnected by a digital net or a contiguous collection of digital nets.
A port whose connections are both digital.
A hierarchical collection of interconnected nets where all the nets are of a discrete discipline.
A user-defined binding of potential and flow natures and other attributes to a net. Disciplines are used to declare analog nets and can also be used as part of the declaration of digital nets.
The process of assigning a domain and discipline to nets whose domain and discipline are otherwise unknown (or whose discipline is wire.)
The context of statements that appear in a location other than an analog block, for example initial and always blocks, in mixed-signal (analog-digital) models such as Verilog-AMS. Anything evaluated by the digital simulator such as process blocks and signal assignment statements, in the VHDL-AMS model.
A net of a discrete discipline.
A variable whose value is calculated in the discrete domain.
The conceptual severing of the connections between drivers and receivers that occurs in mixed nets. When driver-receiver segregation occurs, digital signals propagate only through connect modules inserted between the drivers and receivers.
An expression whose value is derived from the evaluation of a derivative (the ddt
function). Dynamic expressions define time-dependent module behavior. Some functions cannot operate on dynamic expressions.
E
The fundamental unit within a system, which encapsulates behavior and structure (also known as a component).
F
One of the two fundamental quantities used to simulate the behavior of a system. In electrical systems, flow is current.
G
Declarations of variables and parameters at the beginning of a behavioral description.
The reference node, which has a potential of zero.
A named occurrence of a component created from a module definition. One module definition can occur in multiple instances.
The process of creating an instance from a module definition or simulator primitive, and defining the connectivity and parameters of that instance. (Placing an instance in a circuit or system.)
H
A system in which the components are also systems.
K
Physical laws that define the interconnection relationships of nodes, branches, potentials, and flows. Kirchhoff’s Laws specify a conservation of flow in and out of a node and a conservation of potential around a loop of branches.
L
Abbreviation for low-pass filter.
An electronic filter that passes low-frequency signals but attenuates (reduces the amplitude of) signals with frequencies higher than the cutoff frequency.
One block within a behavioral description, delimited by a pair of matching keywords such as begin-end, discipline-enddiscipline.
A component that has no subcomponents.
M
A port with one analog connection and one digital connection.
A hierarchical collection of interconnected nets that includes nets associated with both continuous and discrete disciplines.
A definition of the interfaces and behavior of a component.
N
A named collection of attributes consisting of units, tolerances, and access function names.
Newton-Raphson method. A generalized method for solving systems of nonlinear algebraic equations by breaking them into a series of many small linear operations ideally suited for computer processing.
An expression, which can include registers and variables, and nets of both continuous and discrete disciplines.
A connection point of two or more branches in a graph. In an electrical system, and equipotential surface can be modeled as a node.
An expression whose derivative with respect to time is zero for every point in time.
P
Abbreviation for phase locked loop.
A control system that generates a signal that is related to the phase of an input signal.
A variable used to characterize the behavior of an instance of a module. Parameters are defined in the first section of a module, the module interface declarations, and can be specified each time a module is instantiated.
The statement in a module definition that defines the instance parameters of the module.
The physical connection of an expression in an instantiating (parent) module with an expression in an instantiated (child) module. A port of an instantiated module has two nets, the upper connection, which is a net in the instantiating module, and the lower connection, which is a net in the instantiated module.
One of the two fundamental quantities used to simulate the behavior of a system. In electrical systems, potential is voltage.
A basic component that is defined entirely in terms of behavior, without reference to any other primitives.
A branch introduced into a circuit (or system) that does not alter the circuit’s behavior, but lets the simulator read the potential or flow at that point.
R
Abbreviation for radio frequency.
This is a specific range of an oscillating signal, usually in the 3 KHz-300 GHz range.
Abbreviation for root-mean-squared.
A way to measure the average power.
A convention for determining whether the flow through a branch, the potential across a branch, or the flow in or out of a terminal, is positive or negative.
The global node (which has a potential of zero) against which the potentials of all single nodes are measured. In an electrical system, the reference node is ground.
The conditional introduction and removal of potential and flow sources during a simulation. A potential source can replace a flow source and vice versa.
S
The current nesting level of a block.
A number used to initialize a random number generator, or a string used to initialize a list of automatically generated names, such as for a list of pins.
1. A hierarchical collection of nets that, because of port connections, are contiguous.
2. A single valued function of time, such as voltage or current in a transient simulation.
Instantiating modules inside other modules through the use of module definitions and declarations to create a hierarchical structure in the module’s behavioral description.
A branch introduced between two nodes to contribute to the potential and flow of those nodes.
A collection of interconnected components that produces a response when acted upon by a stimulus.
V
Abbreviation for Voltage Controlled Oscillator.
An oscillator whose frequency can be controlled by a voltage input.
A language for the behavioral description of continuous-time systems that uses a syntax similar to digital Verilog.
A mixed-signal language for the behavioral description of continuous-time and discrete-time systems that uses a syntax similar to digital Verilog.
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