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Contents

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Preface

Related Documents

Internet Mail Address

Typographic and Syntax Conventions

1

Modeling Concepts

Verilog-AMS Language Overview

Describing a System

Analog Systems

Nodes

Conservative Systems

Signal-Flow Systems

Mixed Conservative and Signal-Flow Systems

Simulator Flow for Analog Systems

2

Creating Modules

Declaring Modules

Declaring the Module Interface

Module Name

Ports

Parameters

Specifying Supply Sensitivity Attributes

Using the Sensitivity Attributes in a Chain of Buffers

Using Sensitivity Attributes with Inherited Connections

Defining Module Analog Behavior

Defining Analog Behavior with Control Flow

Using Integration and Differentiation with Analog Signals

Using Internal Nodes in Modules

Using Internal Nodes in Behavioral Definitions

Using Internal Nodes in Higher Order Systems

3

Lexical Conventions

White Space

Comments

Identifiers

Ordinary Identifiers

Escaped Names

Scope Rules

Numbers

Integer Numbers

Real Numbers

Strings

Standard Attributes

4

Data Types and Objects

Output Variables

Integer Numbers

Real Numbers

Converting Real Numbers to Integer Numbers

Strings

Parameters

Specifying a Parameter Type

Specifying Permissible Values

Specifying Parameter Arrays

String Parameters

Parameter Aliases

Dynamic Parameters

Local Parameters

Genvars

Natures

Declaring a Base Nature

Disciplines

Binding Natures with Potential and Flow

Binding Domains with Disciplines

Disciplines and Domains of Wires and Undeclared Nets

Discipline Precedence

Compatibility of Disciplines

Net Disciplines

Ground Nodes

Real Nets

Arrays of Real Nets

Real Nets with More than One Driver

Named Branches

Implicit Branches

5

Statements for the Analog Block

Assignment Statements

Procedural Assignment Statements in the Analog Block

Branch Contribution Statement

Indirect Branch Assignment Statement

Sequential Block Statement

Conditional Statement

Case Statement

Repeat Statement

While Statement

For Statement

Generate Statement

6

Operators for Analog Blocks

Overview of Operators

Unary Operators

Unary Reduction Operators

Binary Operators

Bitwise Operators

Ternary Operator

Operator Precedence

Expression Short-Circuiting

7

Built-In Mathematical Functions

Standard Mathematical Functions

Trigonometric and Hyperbolic Functions

Controlling How Math Domain Errors Are Handled

8

Detecting and Using Events

Detecting and Using Events

Initial_step Event

Final_step Event

Cross Event

Above Event

Absdelta Event

Timer Event

9

Simulator Functions

Announcing Discontinuity

Bounding the Time Step

Announcing and Handling Nonlinearities

Finding When a Signal Is Zero

Querying the Simulation Environment

Obtaining the Current Simulation Time

Obtaining the Current Ambient Temperature

Obtaining the Thermal Voltage

Querying the scale, gmin, and iteration Simulation Parameters

Probing of values Within a Sibling Instance During Simulation

Obtaining and Setting Signal Values

Obtaining Currents Using Out-of-Module References

Accessing Attributes

Examining Drivers

Counting the Number of Drivers

Determining the Value Contribution of a Driver

Determining the Strength of a Driver

Detecting Updates to Drivers

Analysis-Dependent Functions

Determining the Current Analysis Type

Implementing Small-Signal AC Sources

Implementing Small-Signal Noise Sources

Generating Random Numbers

Generating Random Numbers in Specified Distributions

Uniform Distribution

Normal (Gaussian) Distribution

Exponential Distribution

Poisson Distribution

Chi-Square Distribution

Student’s T Distribution

Erlang Distribution

Interpolating with Table Models

Table Model File Format

Example: Using the $table_model Function

Example: Preparing Data in One-Dimensional Array Format

Example: Using $table_model as a Built-In Digital System Task

Node/Net Aliasing System Functions

Aliasing Local Nodes to Hierarchical Nodes with $analog_node_alias

Aliasing Local Nets to Hierarchical Nets with $real_net_alias

Analog Operators

Restrictions on Using Analog Operators

Limited Exponential Function

Time Derivative Operator

Time Integral Operator

Circular Integrator Operator

Derivative Operator

Delay Operator

Transition Filter

Slew Filter

Implementing Laplace Transform S-Domain Filters

Implementing Z-Transform Filters

Displaying Results

$strobe

$display

$write

$debug

$monitor

Specifying Power Consumption

Working with Files

Opening a File

Reading from a File

Writing to a File

Finding the File Position

Closing a File

Simulator Control Functions

$finish

$finish_current_analysis

$stop

$fatal

$error

$warning

$info

Changing the Global Circuit Temperature

Entering Interactive Tcl Mode

User-Defined Functions

Declaring an Analog User-Defined Function

Calling a User-Defined Analog Function

10

Instantiating Modules and Primitives

Instantiating Verilog-AMS Modules

Creating and Naming Instances

Creating Arrays of Instances

Mapping Instance Ports to Module Ports

Connecting the Ports of Module Instances

Port Connection Rules

Overriding Parameter Values in Instances

Overriding Parameter Values from the Instantiation Statement

Overriding Parameter Values Using defparam

Precedence Rules for Overriding Parameter Values

Instantiating Analog Primitives

Instantiating Analog Primitives that Use Array Valued Parameters

Instantiating Modules that Use Unsupported Parameter Types

Using an M Factor (Multiplicity Factor)

Example: Using an M Factor

Including Verilog-A Modules in Spectre Subcircuits

11

Mixed-Signal Aspects of Verilog-AMS

Fundamental Mixed-Signal Concepts

Domains

Contexts

Nets, Nodes, Ports, and Signals

Mixed-signal and Net Disciplines

Behavioral Interaction

Accessing Discrete Nets and Variables from a Continuous Context

Accessing Continuous Nets and Variables from a Discrete Context

Detecting Discrete Events from a Continuous Context

Detecting Continuous Events from a Discrete Context

Connect Modules

Coding Connect Modules

Using Automatically-Inserted Connect Modules

Understanding the Factors Affecting Connect Module Placement

Understanding How Connect Modules Operate

12

Controlling the Compiler

Implementing Text Macros

`define Compiler Directive

`undef Compiler Directive

Compiling Code Conditionally

Including Files at Compilation Time

Adjusting the Time Scale

Setting a Default Discrete Discipline for Signals

Setting Default Rise and Fall Times

Resetting Directives to Default Values

Specifying Which Reserved Keyword List to Use

Removing and Restoring Specific Keywords

Checking Support for Compact Modeling Extensions

A

Nodal Analysis

Kirchhoff’s Laws

Simulating an Analog System

Transient Analysis

Convergence

B

Analog Probes and Sources

Overview of Probes and Sources

Probes

Port Branches

Sources

Unassigned Sources

Switch Branches

Examples of Sources and Probes

Linear Conductor

Linear Resistor

RLC Circuit

Simple Implicit Diode

C

Sample Model Library

Analog Components

Analog Multiplexer

Current Deadband Amplifier

Hard Current Clamp

Hard Voltage Clamp

Open Circuit Fault

Operational Amplifier

Constant Power Sink

Short Circuit Fault

Soft Current Clamp

Soft Voltage Clamp

Self-Tuning Resistor

Untrimmed Capacitor

Untrimmed Inductor

Untrimmed Resistor

Voltage Deadband Amplifier

Voltage-Controlled Variable-Gain Amplifier

Basic Components

Resistor

Capacitor

Inductor

Voltage-Controlled Voltage Source

Current-Controlled Voltage Source

Voltage-Controlled Current Source

Current-Controlled Current Source

Switch

Control Components

Error Calculation Block

Lag Compensator

Lead Compensator

Lead-Lag Compensator

Proportional Controller

Proportional Derivative Controller

Proportional Integral Controller

Proportional Integral Derivative Controller

Logic Components

AND Gate

NAND Gate

OR Gate

NOT Gate

NOR Gate

XOR Gate

XNOR Gate

D-Type Flip-Flop

Clocked JK Flip-Flop

JK-Type Flip-Flop

Level Shifter

RS-Type Flip-Flop

Trigger-Type (Toggle-Type) Flip-Flop

Half Adder

Full Adder

Half Subtractor

Full Subtractor

Parallel Register, 8-Bit

Serial Register, 8-Bit

Electromagnetic Components

DC Motor

Electromagnetic Relay

Three-Phase Motor

Functional Blocks

Amplifier

Comparator

Controlled Integrator

Deadband

Deadband Differential Amplifier

Differential Amplifier (Opamp)

Differential Signal Driver

Differentiator

Flow-to-Value Converter

Rectangular Hysteresis

Integrator

Level Shifter

Limiting Differential Amplifier

Logarithmic Amplifier

Multiplexer

Quantizer

Repeater

Saturating Integrator

Swept Sinusoidal Source

Three-Phase Source

Value-to-Flow Converter

Variable Frequency Sinusoidal Source

Variable-Gain Differential Amplifier

Magnetic Components

Magnetic Core

Magnetic Gap

Magnetic Winding

Two-Phase Transformer

Mathematical Components

Absolute Value

Adder

Adder, 4 Numbers

Cube

Cubic Root

Divider

Exponential Function

Multiplier

Natural Log Function

Polynomial

Power Function

Reciprocal

Signed Number

Square

Square Root

Subtractor

Subtractor, 4 Numbers

Measure Components

ADC, 8-Bit Differential Nonlinearity Measurement

ADC, 8-Bit Integral Nonlinearity Measurement

Ammeter (Current Meter)

DAC, 8-Bit Differential Nonlinearity Measurement

DAC, 8-Bit Integral Nonlinearity Measurement

Delta Probe

Find Event Probe

Find Slope

Frequency Meter

Offset Measurement

Power Meter

Q (Charge) Meter

Sampler

Slew Rate Measurement

Signal Statistics Probe

Voltage Meter

Z (Impedance) Meter

Mechanical Systems

Gearbox

Mechanical Damper

Mechanical Mass

Mechanical Restrainer

Road

Mechanical Spring

Wheel

Mixed-Signal Components

Analog-to-Digital Converter, 8-Bit

Analog-to-Digital Converter, 8-Bit (Ideal)

Decimator

Digital-to-Analog Converter, 8-Bit

Digital-to-Analog Converter, 8-Bit (Ideal)

Sigma-Delta Converter (first-order)

Sample-and-Hold Amplifier (Ideal)

Single Shot

Switched Capacitor Integrator

Power Electronics Components

Full Wave Rectifier, Two Phase

Half Wave Rectifier, Two Phase

Thyristor

Semiconductor Components

Diode

MOS Transistor (Level 1)

MOS Thin-Film Transistor

N JFET Transistor

NPN Bipolar Junction Transistor

Schottky Diode

Telecommunications Components

AM Demodulator

AM Modulator

Attenuator

Audio Source

Bit Error Rate Calculator

Charge Pump

Code Generator, 2-Bit

Code Generator, 4-Bit

Decider

Digital Phase Locked Loop (PLL)

Digital Voltage-Controlled Oscillator

FM Demodulator

FM Modulator

Frequency-Phase Detector

Mixer

Noise Source

PCM Demodulator, 8-Bit

PCM Modulator, 8-Bit

Phase Detector

Phase Locked Loop

PM Demodulator

PM Modulator

QAM 16-ary Demodulator

Quadrature Amplitude 16-ary Modulator

QPSK Demodulator

QPSK Modulator

Random Bit Stream Generator

Transmission Channel

Voltage-Controlled Oscillator

D

Verilog-AMS Keywords

Keywords to Support Backward Compatibility

Discipline and Nature Keywords

Connect Rules Keywords

E

Unsupported Elements of Verilog-AMS

F

Updating Verilog-A Modules

Suggestions for Updating Models

Current Probes

Analog Functions

NULL Statements

inf Used as a Number

Changing Delay to Absdelay

Changing $realtime to $abstime

Changing bound_step to $bound_step

Changing Array Specifications

Chained Assignments Made Illegal

Real Argument Not Supported as Direction Argument

$limexp Changed to limexp

'if 'MACRO is Not Allowed

$warning is Not Allowed

discontinuity Changed to $discontinuity

Glossary

Index

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