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Updating Verilog-A Modules

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The Verilog^®-A language is a subset of Verilog-AMS, but some of the language elements in that subset have changed since Verilog-A was released by itself. As a consequence, you might need to revise your Verilog-A modules before using them as Verilog-AMS modules. The following table highlights the differences.

Feature	Independent Verilog-A	Verilog-AMS	Change type
Analog time	$realtime	$abstime	new
Empty discipline	Predefined as type wire	Type not defined	default definition
Implicit nodes	’default_nodetype discipline_identifier default: wire	default type: empty discipline, no domain type	default definition
initial_step	Default = TRAN	Default = ALL	default definition
final_step	Default = TRAN	Default = ALL	default definition
$realtime	$realtime: timescale =1 sec	$realtime: timescale= ’timescale def=1n. See $abstime	definition
Discontinuity function	discontinuity(x)	$discontinuity(x)	syntax
Limiting exponential function	$limexp(expression)	limexp(expression)	syntax
Port branch access	I(a,a) Cadence® Verilog-A supports only this form.	I(<a>) This form is not supported in Cadence Verilog-A.	syntax
Timestep control (maximum stepsize)	bound_step(const_ expression)	$bound_step(expr)	syntax
Continuous waveform delay	delay()	absdelay()	syntax
User-defined analog functions	Function	Analog function	syntax
Discipline domain	N/A, assumed continuous	Now continuous (default) and discrete	Extension
Time tolerance on timer functions	N/A	Supports additional time tolerance argument for timer()	Extension
Time tolerance on transition filter	N/A	Supports additional time tolerance argument for transition()	Extension
’default_nodetype	’default_nodetype	’default_discipline	Obsolete
Generate statement	generate	N/A	Obsolete
Null statement	;	Limited to case, conditional, and event statements	Obsolete

Suggestions for Updating Models

The remainder of this appendix describes some of these changes in greater detail and suggests ways of modifying your existing Verilog-A models so that they work in version 4.4.6 of Verilog-A and in version 1.0 of Verilog-AMS. The changes recommended here might not work with 4.4.5 or earlier versions of Verilog-A.

Current Probes

OVI Verilog-A 1.0 syntax for a current probe is I(a,a). OVI Verilog-AMS 2.0 changes this to I(<a>).

Suggested change: Put I(<a>) inside an `ifdef __VAMS_ENABLE__, which makes the syntax effective only for Verilog-AMS. For example, change

iin_val = I(vin,vin);

to

`ifdef __VAMS_ENABLE__ 
    iin_val = I(<vin>);   
`else       
    iin_val = I(vin,vin);   
`endif

Verilog-A warning: None

Analog Functions

OVI Verilog-A 1.0 declaration of an analog function is

function name; 

OVI Verilog-AMS 2.0 uses the syntax

analog function name;

Suggested change: Prefix all function declarations by the word analog. For example, change

function real foo;

to

analog function real foo;

Verilog-A warning: None

NULL Statements

OVI Verilog-A 1.0 allows NULL statements to be used anywhere in an analog block. OVI Verilog-AMS 2.0 allows NULL statements to be used only after case statements or event control statements.

Suggested change:

Remove illegal NULL statements. For example, change

begin
end;

to

begin
end

Verilog-A warning: None

inf Used as a Number

Spectre Verilog-A allows 'inf to be used as a number. OVI Verilog-AMS 2.0 allows 'inf to be used only on ranges.

Suggested change:

Change all illegal references to 'inf to a large number such as 1M. For example, change;

parameter real points_per_cycle = inf from [6:inf];

to

parameter real points_per_cycle = 1M from [6:inf];

Verilog-A warning: None

Changing Delay to Absdelay

OVI Verilog-A 1.0 uses delay as the analog delay operator but OVI Verilog-AMS 2.0 uses absdelay.

Suggested change: Change delay to absdelay. This change usually leads to faster, better results.

Verilog-A warning: None

Changing $realtime to $abstime

OVI Verilog-A 1.0 uses $realtime as absolute time but OVI Verilog-AMS 2.0 uses $abstime.

Suggested change: Change $realtime to $abstime.

Verilog-A warning: Yes

Changing bound_step to $bound_step

OVI Verilog-A 1.0 uses bound_step for step bounding but OVI Verilog-AMS 2.0 uses $bound_step.

Suggested change: Change bound_step to $bound_step.

Verilog-A warning: None

Changing Array Specifications

OVI Verilog-A 1.0 uses [] to specify arrays but OVI Verilog-AMS 2.0 uses {}.

Suggested change: Change [] to {}. For example, change

svcvs #(.poles([-2*`PI*bw,0])) output_filter

to

svcvs #(.poles({-2*`PI*bw,0})) output_filter

Verilog-A warning: None

Chained Assignments Made Illegal

Spectre-Verilog-A allows chained assignments, such as x=y=z, but OVI Verilog-AMS 2.0 makes this illegal.

Suggested change: Break chain assignments into single assignments. For example, change

x=y=z;

to

y = z; x = y;

Verilog-A warning: None

Real Argument Not Supported as Direction Argument

Spectre-Verilog-A allows real numbers to be used for the arguments of @cross and last_crossing but OVI Verilog-AMS 2.0 makes this illegal.

Suggested change: Change the real numbers to integers. For example, change

@(cross(V(in),1.0) begin

to

@(cross(V(in),1) begin

Verilog-A warning: None

$limexp Changed to limexp

OVI Verilog-A 1.0 uses $limexp, but OVI Verilog-AMS 2.0 uses limexp.

Suggested change: Change $limexp to limexp. For example, change

I(vp,vn) <+ is * ($limexp(vacross/$vt) - 1);

to

I(vp,vn) <+ is * (limexp(vacross/$vt) - 1);

Verilog-A warning: None

'if 'MACRO is Not Allowed

Spectre-Verilog-A allows users to type 'if 'MACRO, but OVI Verilog-AMS 2.0, 1.0 and 1364 say this is illegal.

Suggested change: Change 'if 'MACRO to 'if MACRO (Do not use the tick mark for the macro). For example, change

`ifdef `CHECK_BACK_SURFACE

to

`ifdef CHECK_BACK_SURFACE

Verilog-A warning: None

$warning is Not Allowed

Spectre-Verilog-A supports $warning, but OVI Verilog-AMS 2.0, 1.0 and 1364 do not support this as a standard built-in function.

Suggested change: Change $warning to $strobe.

Verilog-A warning: None

discontinuity Changed to $discontinuity

OVI Verilog-A 1.0 uses discontinuity, but OVI Verilog-AMS 2.0 uses $discontinuity.

Suggested change: Change discontinuity to $discontinuity.

Verilog-A warning: None

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