Product Documentation
Cadence Verilog-AMS Language Reference
Product Version 22.09, April 2022

3


Lexical Conventions

A Cadence® Verilog®-AMS source text file is a stream of lexical tokens arranged in free format. For information, see, in this chapter,

See also

White Space

White space consists of blanks, tabs, new-line characters, and form feeds. Verilog-AMS ignores these characters except in strings or when they separate other tokens. For example, this code fragment

$strobe("bit error rate = %f%%",
    100.0 * errors / bits ) ;

is syntactically identical to:

$strobe("bit error rate = %f%%",100.0*errors/bits);

Comments

In Verilog-AMS, you can designate a comment in either of two ways.

Identifiers

You use an identifier to give a unique name to an object, such as a variable declaration or a module, so that the object can be referenced from other places. There are two kinds of identifiers: ordinary identifiers and escaped names. Both kinds are case sensitive.

Ordinary Identifiers

The first character of an ordinary identifier must be a letter or an underscore character (_), but the remaining characters can be any sequence of letters, digits, dollar signs ($), and the underscore. Examples include

unity_gain_bandwidth
holdValue
HoldTime
_bus$2

Escaped Names

Escaped names start with the backslash character (\) and end with white space. Neither the backslash character nor the terminating white space is part of the identifier. Therefore, the escaped name \pin2 is the same as the ordinary identifier pin2.

An escaped name can include any of the printable ASCII characters (the decimal values 33 through 126 or the hexadecimal values 21 through 7E). Examples of escaped names include

\busa+index
\-clock
\!!!error-condition!!!
\net1\\net2
\{a,b}
\a*(b+c)

Scope Rules

In Verilog-AMS, each module, task, function, analog function, and named block that you define creates a new scope. Within a scope, an identifier can declare only one item. This rule means that within a scope you cannot declare two variables with the same name, nor can you give an instance the same name as a node connecting that instance.

Any object referenced from a named block must be declared in one of the following places.

To find a referenced object, the simulator first searches the local scope. If the referenced object is not found in the local scope, the simulator moves up the name tree, searching through containing named blocks until the object is found or the module boundary is reached. If the module boundary is reached before the object is found, the simulator issues an error.

Numbers

Verilog-AMS supports two basic literal data types for arithmetic operations: integer numbers and real numbers.

Integer Numbers

The syntax for an integer constant is

integer_number ::= 
        [ sign ] unsign_num
    |   digital_octal_number
    |   digital_binary_number
    |   digital_hex_number
sign ::= 
   + | -
unsign_num ::=  
        decimal_digit { _ | decimal_digit }
decimal_digit ::= 
   0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9

For information about digital_octal_number, digital_binary_number, and digital_hex_number, see the “Numbers” section in the “Lexical Conventions” chapter, of the Verilog-XL Reference

The simulator ignores the underscore character ( _ ), so you can use it anywhere in a decimal number except as the first character. Using the underscore character can make long numbers more legible.

Examples of integer constants include

277195000
277_195_000 //Same as the previous number
-634 //A negative number
0005
’b100x11z0   //A binary number with unknowns

Real Numbers

The syntax for a real constant is

real_number ::=
        [ sign ] unsign_num .unsign_num
    |   [ sign ] unsign_num [.unsign_num] e [ sign ] unsign_num
    |   [ sign ] unsign_num [.unsign_num] E [ sign ] unsign_num
    |   [ sign ] unsign_num [.unsign_num ] unit_letter
sign ::= 
   + | -
unsign_num ::=  
        decimal_digit { _ | decimal_digit }
decimal_digit ::= 
   0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
unit_letter ::=
        T | G | M | K | P | k | m | u | n | p | f | a

unit_letter represents one of the scale factors listed in the following table. If you use unit_letter, you must not have any white space between the number and the letter. Be certain that you use the correct case for the unit_letter.

unit_letter Scale factor unit_letter Scale factor

T =

1012

k =

103

G =

109

m =

10-3

M =

106

u =

10-6

K =

103

n =

10-9

P=

1015

p =

10-12

f =

10-15

a =

10-18

The simulator ignores the underscore character ( _ ), so you can use it anywhere in a real number except as the first character. Using the underscore character can make long numbers more legible.

Examples of real constants include

2.5K              // 2500
1e-6 // 0.000001
-9.6e9
-1e-4
0.1u
50p // 50 * 10e-12
1.2G // 1.2 * 10e9
213_116.223_642

For information on converting real numbers to integer numbers, see “Converting Real Numbers to Integer Numbers”.

Strings

A string is a sequence of characters enclosed by quotation marks and contained on a single line. Strings used as operands in expressions and assignments are treated as unsigned integer constants represented by a sequence of 8-bit ASCII values, with one 8-bit ASCII value representing one character.

String variables, which are not supported in analog contexts, are variables of reg type with width equal to the number of characters in the string multiplied by 8.

For example, to store the 12 characters of the string “Hello world!” requires a reg 8 * 12, or 96 bits wide.

reg [8*12:1] stringvar ;
initial begin
    stringvar = “Hello world!” ;
end

When a variable is larger than required to hold a value being assigned, the contents on the left are padded with zeros after the assignment. This is consistent with the padding that occurs during the assignment of nonstring values. If a string is larger than the destination string variable, the string is truncated to the left, and the leftmost characters are lost.

Strings can be manipulated using the Verilog HDL operators. The value being manipulated by the operator is the sequence of 8-bit ASCII values. For example,

module string_test; 
reg [8*14:1] stringvar;
initial begin
stringvar = "Hello world";
$display("%s is stored as %h", stringvar,stringvar);
stringvar = {stringvar,"!!!"};
$display("%s is stored as %h", stringvar,stringvar);
end
endmodule

The output is

Hello world is stored as 00000048656c6c6f20776f726c64
Hello world!!! is stored as 48656c6c6f20776f726c64212121

Standard Attributes

The standard attributes for descriptions and units have a special meaning for variables declared at module scope. Module scope variables with a description or units attribute, or both, are known as output variables and Cadence tools provide access to their values. Also, Cadence tools print the names, values, units, and descriptions of output variables for primitives when displaying operating-point information.

The standard attribute op specifies whether or not a parameter or a variable should be included in the report containing the most useful operating point values. You must specify either yes or no as a value to the attribute. If you specify yes as the value, the parameter or variable is included in the report.

The standard attribute multiplicity scales the value of the parameter or variable for reporting. You must specify one of the following as a value to the attribute: multiply, divide, or none. If you specify multiply as a value to the attribute, the value of the parameter or variable is multiplied by the value of $mfactor for the instance in any report of operating-point values. If you specify divide as a value to the attribute, the value of the parameter or variable is divided by the value of $mfactor for the instance in any report of operating-point values. If you do not specify any value for the attribute, or specify none as a value, scaling is not performed.

In this release, the multiplicity attribute behaves as though the attribute is assigned the value none, regardless of the value you actually use. This means that no scaling is performed when you use the multiplicity attribute.

For example, a module for a MOS transistor with the following declaration at module scope provides the

output variable cgs.
(* desc="gate-source capacitance", units="F" *)
real cgs;

An operating-point display from Cadence tools includes the following information:

cgs=4.21e-15 F

Descriptions for instance parameters of mos_inst:

cgs: gate-source capacitance

Units and descriptions specified for block-level variables are ignored by the simulator, but can be used for documentation purposes.


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