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Preface

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This manual describes the analog and mixed-signal aspects of the Cadence^® Verilog^®-AMS language. With Verilog-AMS, you can create and use modules that describe the high-level behavior and structure of analog, digital, and mixed-signal components and systems. The guidance given here is designed for users who are familiar with the development, design, and simulation of circuits and with high-level programming languages, such as C.

For information about the digital aspects of Verilog-AMS, the definitive source is IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language (IEEE Std 1364-1995), published by the IEEE. Cadence documents that describe digital Verilog include the NC Verilog Simulator Help and the Verilog-XL Reference.

The preface discusses the following:

• Related Documents
• Internet Mail Address
• Typographic and Syntax Conventions

Related Documents

For more information about Verilog-AMS and related products, consult the sources listed below.

• Virtuoso AMS Designer Environment User Guide
• Virtuoso AMS Designer Simulator User Guide
• Virtuoso Analog Design Environment User Guide
• Virtuoso Mixed-Signal Circuit Design Environment User Guide
• SimVision Analysis Environment User Guide
• Virtuoso Spectre Circuit Simulator Reference
• Virtuoso Spectre Circuit Simulator User Guide
• Verilog-A Debugging Tool User Guide
• Cadence Verilog-A Language Reference
• Cadence Hierarchy Editor User Guide
• Component Description Format User Guide
• IEEE Standard VHDL Language Reference Manual (Integrated with VHDL-AMS Changes), IEEE Std 1076.1. Available from IEEE.
• Instance-Based View Switching Application Note
• Cadence Library Manager User Guide
• Signalscan Waves User Guide
• Virtuoso Schematic Editor User Guide
• Verilog-AMS Language Reference Manual. Available from Open Verilog International.
• Verilog-XL Reference

Internet Mail Address

You can send product enhancement requests and report obscure problems to Customer Support. For current phone numbers and e-mail addresses, go to Cadence Online Support and click the Contact Us link on the Home page.

For help with obscure problems, please include the following in your e-mail:

• The license server host ID
  To determine what your server’s host ID is, use the Subscription Service of Cadence Online Support for assistance.
• A description of the problem
• The version of the Verilog-AMS product that you are using
  The version of the Verilog-AMS product described here is 1.0.
• Analog simulation control files, top-level modules and all included files including hardware design language (HDL) modules so that Customer Support can reproduce the problem
• Output logs and error messages

Typographic and Syntax Conventions

Special typographical conventions are used to distinguish certain kinds of text in this document. The formal syntax used in this reference uses the definition operator, ::= , to define the more complex elements of the Verilog-AMS language in terms of less complex elements.

• Lowercase words represent syntactic categories. For example,
  

  module_declaration

  Some names begin with a part that indicates how the name is used. For example,

  node_identifier

  represents an identifier that is used to declare or reference a node.
• Boldface words represent elements of the syntax that must be used exactly as presented. Such items include keywords, operators, and punctuation marks. For example,
  

  endmodule

• Vertical bars indicate alternatives. You can choose to use any one of the items separated by the bars. For example,
  

  attribute ::=
       abstol
   |   access
   |   ddt_nature
   |   idt_nature
   |   units
   |   huge
   |   blowup
   |   identifier

• Square brackets enclose optional items. For example,
  

  input declaration ::=
   input [ range ] list_of_port_identifiers ;

• Braces enclose an item that can be repeated zero or more times. For example,
  

  list_of_ports ::=
   ( port { , port } )

Code examples are displayed in constant-width font.

/* This is an example of the font used for code.*/ 

Within the text, variables are in italic font, like this: allowed_errors.

Within the text, keywords, filenames, names of natures, and names of disciplines are set in constant-width font, like this: keyword, file_name, name_of_nature, name_of_discipline.

If a statement is too long to fit on one line, the remainder of the statement is indented on the next line, like this:

qgf = width*length*cfbb*(vgfs - wkf - qb/(2*cbb) - 
        (vgbs - vfbb + qb/(2*cob))) + qgf_par ;

To distinguish Verilog-AMS modules from the contents of analog simulation control files, the latter are enclosed in boxes and include a comment line at the beginning identifying them as analog simulation control files.

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