Classification of Modules in Verilog In

This topic describes the following details:

• Classification of modules
• Guidelines for modifying your design
• Guidelines for creating schematic symbols
• Imports of modules in Verilog In
• Escaped name mapping
• Parameters and defparams handling by Verilog In
• Reasons behind failure of importing data
• Miscellaneous problems

Verilog HDL format is a textual description of the design. This format describes each design as a collection of modules. For each module in the design, Verilog In creates a cell in the Virtuoso Studio Design Environment library. Verilog In checks each module and decides if it is one of the following:

• A behavioral cell module, which is a module defined as a set of procedures
• A structural cell module, which is an interconnection of instances
• A Verilog HDL cell module

Verilog In treats User-Defined Primitives (UDPs) like modules. Regardless of the type of module, the imported design retains its connectivity between module instances.

Behavioral Cell Modules

If the module is behavioral, Verilog In imports it into a functional view and a symbol view. Verilog In decides that a module is behavioral if importing the module as a schematic does not capture all the information in the HDL description. In this case, the netlister might not be able to regenerate the HDL description from the schematic view of the module. Accordingly, Verilog In considers a module to be behavioral if any of the following is true:

• The module has a specify block statement
• The module has an instance of the cds_alias module (Verilog In treats the cds_alias module as a special case.)
• The module has global or scoped nets
• The module has a child with multiple ports with the same name
• The module has an expression on a port
• The module has strengths defined for a gate
• The module has a task call, function call, or declaration
• The module has a delay statement
• The module has any behavioral statement
• The module has a reg declaration
• The module has compiler directives. Note the exceptions described below:

A module is not always considered behavioral only because it has compiler directives. When a schematic is generated for a module that has compiler directives, all the compiler directives are ignored except 'timescale, which is added as a property on the schematic, 'define, and 'ifdef.

The 'include and 'define compiler directives are not always considered behavioral. See Guidelines for Design Modification in Verilog In.

Structural Cell Modules

If the module is structural, Verilog In imports it into a schematic view and a symbol view. Verilog In decides a module is structural if it has only the following types of statements:

• Module or UDP instantiations
• Gate instantiations
• Input and output ports, and wire net declarations

If the module has behavioral statements or is classified as behavioral, it is imported as a functional view.

Verilog HDL Cell Modules

If the module is a Verilog HDL cell, Verilog In uses the Verilog Cell Modules option on the Verilog In form to import the module as a functional view and create a symbol for it. If insufficient information is provided in the module to create a functional view, Verilog In creates only the symbol.

Verilog In decides a module is a Verilog HDL cell if it meets one of the following conditions:

• The module definition is in a -y directory or -v file, and the Verilog option +nolibcell is not specified.
• A 'celldefine compiler directive precedes the module.

For the description of a Verilog HDL cell, see the Verilog-XL Reference.

Related Topics

Guidelines for Design Modification in Verilog In.

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