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Introduction
What is VHDL-AMS?
The VHDL language has been extended to support analog and mixed-signal design. This extension is referred to as VHDL-AMS and is defined in the IEEE 1076.1 standard. The extensions to the core IEEE 1076 standard support analog behavioral modeling. These extensions support both conservative system and signal flow system semantics.
When you use the Cadence AMS Designer environment, you can directly instantiate textual VHDL-AMS views — along with VHDL (digital), Verilog-A, Verilog-AMS, Verilog (digital), and Spectre primitive views — from within the Virtuoso schematic composer tool.
Extensions to VHDL
Since VHDL first became a standard, a number of extensions have been added to the language. These extensions allow the language to be used for digital synthesis, gate level simulation, and now analog and mixed-signal modeling and simulation.
The Cadence solution currently supports the following extensions:
- ANSI/IEEE Std 1076-1993, IEEE standard VHDL Language Reference Manual
- IEEE Std 1076-1987 IEEE, standard VHDL Language Reference Manual
- IEEE Std 1076.1-1999 IEEE, standard VHDL Analog and Mixed-signal Extensions
- IEEE Std 1076.2-1996 IEEE, Standard VHDL Mathematical Packages
- IEEE Std 1076.3-1997 IEEE, Standard VHDL Synthesis Packages
- IEEE Std 1076.4-2000, IEEE standard for VITAL ASIC (application specific integrated circuit) Modeling Specification
- IEEE Std 1076.6-1999, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis
If you plan to use VHDL for digital synthesis, be aware that digital synthesis tools support only the subset of the language specified by the 1076.6-1999 and 1076.3-1997 extensions.
Benefits of VHDL-AMS
VHDL-AMS provides many benefits, including:
- The ability to model discrete and continuous time systems at various levels of abstraction. Most of the constructs required for modeling are built into the language; others are provided by standardized packages.
- Support for a variety of modeling styles, including dataflow modeling, modeling conservative systems, and creating structural designs. The support that VHDL-AMS provides for simulation, description, and digital synthesis means the language is useful throughout the design cycle. The ability to describe designs at the data flow and analog behavioral levels allows you to concentrate on the concept of the design rather than on low level details.
- Support for analog behavioral models, which allow for significantly faster simulations at the system level.
- The ability to access libraries of predefined components.
- Support for packages, which facilitates sharing a group of design data, types, functions, and procedures under a single name.
- Support for hierarchies, so that design entities can be instantiated within other design entities as components. The process of binding design entities to the component references in hierarchical descriptions supports an iterative, fluid approach to development.
- Support for binding components with entity architecture pairs under the control of configurations. Both Cadence configurations and VHDL configurations are supported.
- Wide support and portability to other design environments. The fact that VHDL-AMS is non-proprietary means that there is a large selection of VHDL and VHDL-AMS models available.
- The ability, when using the AMS Designer environment, to incorporate and simulate two standard, public languages (VHDL-AMS and Verilog-AMS) in the same design.
- Support for bottom-up verification, which allows for faster full chip verification.
Implications of Using VHDL-AMS
The potential lifetime of a design is extended beyond the lifetime of the underlying hardware technology, protecting against technology changes. A shorter development time is also likely due to the ability to verify design concepts before deciding on hardware.
Textual descriptions augment schematics by allowing definition of the behavior of a cell rather than just selecting predefined cells from a library.
VHDL-AMS promotes the use of more simulation during the development phase, allowing designers to explore a wider set of alternative solutions to a given problem.
Adopting a consistent style of coding with the ability to make modifications quickly encourages designers to share their models and designs thus increasing IP reuse. Further advantages are also found as you consider digital synthesis, design for test, and characterization solutions.
References to the VHDL-AMS Language Reference
This document refers frequently to the IEEE Standard VHDL Analog and Mixed-Signal Extensions Language Reference, using a notation like, “See LRM 3.2,” where the numbers indicate the relevant section and subsection in the reference.
Using VHDL-AMS with Other Languages
For more information about using VHDL-AMS with other languages in a mixed-signal design, see chapter 4, “Preparing the Design: Using Mixed Languages,” in Virtuoso AMS Designer Simulator User Guide.
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