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Preface

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This manual describes the analog and mixed-signal aspects of the Cadence^® VHDL-AMS language. With VHDL-AMS, you can create and use modules that describe the high-level behavior and structure of analog, digital, and mixed-signal components and systems. The guidance given here is designed for users who are familiar with the development, design, and simulation of circuits and with high-level programming languages.

The preface discusses the following:

• Related Documents
• Internet Mail Address
• Typographic and Syntax Conventions

Related Documents

For more information about VHDL-AMS and related products, consult the sources listed below.

• Cadence AMS Designer Environment User Guide
• Cadence AMS Designer Simulator User Guide
• Virtuoso Analog Design Environment User Guide
• Virtuoso Mixed-Signal Circuit Design Environment User Guide
• SimVision Analysis Environment User Guide
• Spectre Circuit Simulator Reference
• Spectre Circuit Simulator User Guide
• Cadence Hierarchy Editor User Guide
• Component Description Format User Guide
• IEEE Standard VHDL Analog and Mixed-Signal Extensions, IEEE Std 1076.1-1999. Available from IEEE.
• Instance-Based View Switching Application Note
• Cadence Library Manager User Guide
• Virtuoso Schematic Composer User Guide

Internet Mail Address

You can send product enhancement requests and report problems to Customer Support. For current phone numbers and e-mail addresses, go to Cadence Online Support and click the Contact Us link on the Home page.

Please include the following in your e-mail:

• The license server host ID
  To determine what your server’s host ID is, use the Subscription Service of Cadence Online Support for assistance.
• A description of the problem
• The version of the VHDL-AMS product that you are using
• Analog simulation control files, top-level modules and all included files including hardware design language (HDL) modules so that Customer Support can reproduce the problem
• Output logs and error messages

Typographic and Syntax Conventions

Special typographical conventions distinguish certain kinds of text in this document. The formal syntax in this reference uses the definition operator, ::=, to define the more complex elements of the VHDL-AMS language in terms of less complex elements.

• Lowercase words represent syntactic categories. For example,
  

  module_declaration

  Some names begin with a part that indicates how the name is used. For example,

  node_identifier

  represents an identifier that is used to declare or reference a node.
• Boldface words represent elements of the syntax that must be used exactly as presented. Such items include keywords, operators, and punctuation marks. For example,
  

  
  end block
  

• Vertical bars indicate alternatives. You can choose to use any one of the items separated by the bars. For example,
  

  logical_operator ::=
       
  and
  
   |   
  or
  
   |   
  nand
  
   |   
  nor
  
   |   
  xor
  
   |   
  xnor
  

• Square brackets enclose optional items. For example,
  

  subprogram_body ::=
   [pure|impure]

• Braces enclose an item that can be repeated zero or more times. For example,
  

  architecture_body ::=
   architecture identifier of entity_name is
    {block_declarative_part}

Code examples are displayed in constant-width font.

---This is an example of the font used for code.

Within the text, variables are in italic font, like this: allowed_errors.

Within the text, keywords, reserved words and filenames are set in constant-width font, like this: reserved_word, file_name

If a statement is too long to fit on one line, the remainder of the statement is indented on the next line, like this:

qgf = width*length*cfbb*(vgfs - wkf - qb/(2*cbb) - 
        (vgbs - vfbb + qb/(2*cob))) + qgf_par ;

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