2 VHDL-AMS Modeling Styles

You can read about the following topics in this chapter:

Levels of Abstraction

Design abstraction is a strategy for managing complexity and hiding and showing details. At lower levels of abstraction, more details are exposed and the behavior of the model is closer to the complexity of the physical implementation of a design. At higher levels of abstraction, less detail is exposed and the behavior of the model is further from the physical implementation of the design. Typically, designs using higher levels of abstraction simulate faster that designs using lower levels of abstraction.

VHDL-AMS provides blocks that you can use to partition and organize designs into hierarchies. Multiple levels of nested blocks are allowed. The internal details of these relationships can be shown or hidden from view, as desired. The hierarchy consists of behavioral and structural elements. The structural elements define the parent/child relationships. As illustrated in the following diagram, these relationships can be represented as a tree structure

Analog Abstraction Hierarchy

The tables below list the levels of abstraction most often associated with analog circuits.

Table 2-1 Abstraction Hierarchy for the Analog Functional Domain
Level	Description
Functional or behavioral signal flow	Describes signal flow input/output relations by mathematical functions. For example, you might model an op-amp as an output that is a function of its input.
Functional or behavioral conservative	Uses equations to describe relations between terminals. You might use this level of abstraction to model a capacitor that takes second order effects into account.
Ideal equations	Uses idealized device models
Characteristic equations	Uses device models that include second order effects

Table 2-2 Abstraction Hierarchy for the Analog Structural Domain
Level	Description
System transfer functions	Models signal flow between system level blocks
Macro Models	Uses a parameterizable block of device models to model some complex function
Ideal sources and devices	Uses idealized device models
Nets and devices	Uses primitive devices and wire models that include second order effects

Conservative Systems

A conservative system is one that obeys the laws of conservation described by Kirchhoff’s Potential and Flow laws. Across quantities define the potential between two terminals. Through quantities define the flow through a terminal (to another terminal).

Terminals

A terminal is a point of physical connection between devices of continuous-time descriptions. Terminals obey conservation-law semantics.

Reference Terminal

The potential of a single terminal is defined with respect to a reference terminal. The reference terminal, often called ground in electrical systems, has a potential of zero.

NATURE electrical IS voltage ACROSS current THROUGH ground REFERENCE;

The reference terminal is declared as part of the nature declaration, can have any name, but is a unique terminal. A terminal (node in Verilog) cannot be arbitrarily declared to be the reference. See LRM 4.8.

Reference Directions

Each branch quantity has a reference direction. For example, consider the following schematic. With the reference direction shown, the potential in this schematic is positive whenever the potential of the terminal marked with a plus sign is larger than the potential of the terminal marked with a minus sign.

The direction of a branch quantity is determined by the order of the terminals in the terminal_aspect of the branch quantity declaration. See LRM 4.3.1.6. So, for example:

QUANTITY vx ACROSS ix THROUGH t1 TO t2;

declares an across quantity vx from terminal t1 to terminal t2. The value of vx is positive if terminal t1 has a higher potential than terminal t2 (it would be negative if t2 had a higher potential than t1). It also declares a through quantity ix through t1 to t2. If the flow is from t1 to t2 then the value of ix is positive (if the flow is from t2 to t1 then the value of ix is negative). If we change the declaration to:

QUANTITY vx ACROSS ix THROUGH t2 TO t1;

the value of vx and ix change signs.

Analog Systems

For analog systems, the simulator uses Kirchhoff’s laws to develop equations that define the values and flows in the system. Because the equations can be differential and nonlinear, the simulator does not solve them directly. Instead, the simulator uses an approximation and solves the equations iteratively at individual time points (also called solution points). The simulator controls the interval between the time points to ensure the accuracy of the approximation.

At each time point, iteration continues until two convergence criteria are satisfied. The first criterion requires that the approximate solution on this iteration be close to the accepted solution on the previous iteration. The second criterion requires that Kirchhoff’s Flow Law be adequately satisfied. To determine the required accuracy for these criteria, the simulator uses the tolerances specified in the design.

An analog model contains three equation sets: the explicit set, the structural set, and the augmentation set. The explicit set is derived from the simultaneous statements that describe the signal flow behavior of free quantities and the branch behavior of branch quantities. The structural set, which is derived from Kirchoff’s Laws, constrains a network of branches to obey conservation of charge and potential. The augmentation set describes how ’DOT and ’INTEG are defined under various conditions such as computing initial state or solving a time integration step. At each solution point, the analog solver finds a simultaneous solution to the combined equations from all three sets.

Simultaneous Statements

Simultaneous statements are algebraic and differential equations used to define the analog behavior of a system. For example:

simple_expression == simple_expression;

simple-expression can contain linear, nonlinear, or differential equations involving operations on any value bearing construct (such as quantities, variables, constants, attributes, and arrays of constants, generics or signals).

For example, the following signal flow description produces the sum and product of its inputs:

entity am is 
    port(quantity in1, in2: in real; quantity outsum, outmult: out real); 
end am;

architecture am_behav of am is 
begin 
    outsum == in1 + in2; 
    outmult == in1 * in2; 
end am_behav;

You can define dynamic relationships between the inputs and outputs of modules. For example, here is a conservative model behavioral description for a capacitor:

entity cap is 
    generic(c : real := 1.0e-3); 
    port (TERMINAL n, p: electrical); 
end cap;

architecture cap_behav of cap is 
    quantity vcap across icap through n to p; 
begin 
    icap == vcap’dot * c; 
end cap_behav;

The ’integ attribute is used to relate quantities to time integrals of other quantities. For example, the following signal flow model sets the output to the integral of the input (with respect to time). The break statement specifies the initial conditions on input’integ, which are needed during DC analysis.

entity integrator is 
    port (quantity input: in real; quantity output : out real); 
end integrator; 

architecture integrator_behav of integrator is 
begin 
    break input’integ => 0.0; 
    output == input’integ; 
end integrator_behav;

You can perform index and slice operations on signal arrays in simultaneous equations.
For example:

Signal s : real_vector(0 to 3) := (0.0, 0.0, 0.0, 0.0); 
Quantity q1 : real_vector (0 to 3); 
Quantity  q2 : real; 
q1 == s; 
q2 == s(2);

If you are using the Spectre or UltraSim solver with the simulation front end (SFE) parser, you can also perform index and slice operations on constant and generic arrays in simultaneous equations. For example:

s == paramB( 1 downto 0 );

The array slice must have the same direction (such as downto) as the array declaration.

You can perform index and slice operations on constant, generic, and signal arrays only in simultaneous statements. You must be using the SFE parser in order to use constant and generic arrays in this way.

You can assign a whole quantity array to a whole constant, generic, or signal array.
For example:

r == paramA;

You can access individual bits of a constant, generic, or signal array using another constant (such as constIndex here):

t == paramB( constIndex );

In an analog context (and using the SFE parser), you can pass the result of a constant or generic indexed expression to a user-defined function. For example:

x == addParams( q(0) - paramB(0), q(1) + paramB(1) );

Conditional Behavior in Simultaneous Statements

You can use simultaneous conditional statements to define behavior in regions. The following architecture describes a voltage deadband amplifier vdba. For example, the conditional if-else structure describes the piecewise linear approximation of the characteristics of the amplifier. If the input voltage is greater than vin_high or less than vin_low, the amplifier is active. When the amplifier is active, the output is the gain times the differential voltage between the input voltage and the edge of the deadband. When the input is in the deadband between vin_low and vin_high, the amplifier is quiescent, and the output voltage is zero.

ENTITY vdba IS
    GENERIC (vin_low : REAL := -2.0; vin_high : REAL := 2.0; gain : REAL := 1.0);
    PORT (QUANTITY input : IN REAL; QUANTITY output : OUT REAL);
END vdba;

ARCHITECTURE vdba_behav OF vdba IS
BEGIN
    IF (input >= vin_high) USE
     output == gain * (input - vin_high);
 ELSIF (input <= vin_low) USE
  output == gain * (input - vin_low);
 ELSE
  output == 0.0;
 END USE;
END vdba_behav;

The following graph shows the response of the amplifier to a sinusoidal source.

Design Hierarchy

Hierarchy is supported by means of instantiation, which refers to the process of creating an instance of a design entity inside another design entity. Such instances are referred to as components.

Here is an example of an architecture that contains component instantiation.

ENTITY rc IS
    PORT (TERMINAL t1, t2: electrical);
END rc;

ARCHITECTURE rc_behav OF rc IS
    component cap IS
     port (terminal t1, t2: electrical);
  generic (rval : real := 1.0e-3);
 end component;
 for all : cap_comp use entity work.cap(cap_behav);
 component resistor is
  port (terminal t1, t2: electrical);
  generic (cval := real := 1000.0);
 end component;
 for all : resistor_comp use entity work.resistor(resistor_behav);
 r1: resistor_comp
  generic map(2000.0)
  port map(t1, t2);
 c1 : capacitor_comp
  generic map (2.0e-3)
  port map(t2, gnd);
END rc_behav;

Digital Abstraction Hierarchy

Just as analog blocks have different levels of abstraction, digital models can also be categorized according to their level of abstraction. The following table shows the abstraction hierarchy associated with digital models and systems.

Level	Modeling Method	Structural Primitive	Time Model
System level	Cooperating processing units	CPU, memory, bus	Causality
Chip level	Parallel algorithms	Controller, RAM, ROM, UART	Discrete (fine/coarse granularity)
Register transfer level	Guarded commands	Register, counter, ALU, multiplexor	Discrete (coarse granularity)
Logic gate level	Boolean logic equations	Gate, flip-flop	Discrete (fine granularity)
Circuit level	Differential equations	Transistor, R, L, C	Continuous

A digital description can use several of these different styles simultaneously.

System Level

As the name suggests, a system-level design can describe a complete system, comprising multiple PCBs connected to a backplane bus, although a system level description does not always contain a vast amount of structural information. In addition to the models of the hardware components making up a system, system-level designs often model the bus systems or networks used to interconnect the components. For example, a VHDL description of a computer interface card might be verified by using a VHDL model of the computer system bus and connecting the two of them together to form a testbench.

Chip Level

Chip-level VHDL descriptions fall into two general categories: those intended for synthesis, and those intended for simulation. The first category consists of RTL descriptions forming a top-level structure without any detailed timing information other than basic clocking relationships. The chip being described is typically an FPGA or cell-based ASIC.

The second category of chip-level descriptions are those intended for simulation. These descriptions are primarily behavioral models whose purpose is to accurately simulate the behavior of the chip at the pin level. The internal organization of the model is not important. To achieve this, the models generally include detailed timing behavior, extracted from the manufacturer's data sheets, concerning the behavior of the device interface pins under most conditions.

Many IC manufacturers are producing accurate VHDL models for their standard devices. Models are available for a large range of devices covering simple gates to full-blown microprocessors. The primary purpose of these models is to enable a designer to perform a realistic simulation of a full system.

Register Transfer Level

Register transfer level (RTL) descriptions are the most commonly used style of VHDL description. At this level, systems are described in terms of combinational and sequential functions at the behavioral level. The functions are often described using individual processes and interconnected using signals to form a dataflow. Typical functions included in an RTL description are registers, counters, and state machines along with combinational functions such as multiplexors, arithmetic units, and decoders. The RTL style can include some structural information via the dataflow. However, the individual functional blocks are described using behavioral constructs rather than instantiated gates and flip-flops. Many designs consist of registers interspersed with combinational functions and together these form the datapath. Transfers between registers and operations carried out by combinational functions are controlled by the controller or control path, which is usually a behavioral description of a finite state machine.

The RTL level of description is particularly relevant to users of logic synthesis, because this is the accepted level for designs that are intended for synthesis.

Logic Gate Level

VHDL-AMS provides many features for the support of gate-level simulation, the most useful being the Boolean operators (AND, OR, XOR, etc.), which correspond directly to the gate-level primitives. Boolean circuit algebra does not directly address the important delay time of the components so time values must be attributed by additional models.

In addition to basic logic gates, this level includes other low-level primitives such as flip-flops and latches. VHDL-AMS descriptions written at this level are referred to as netlists or wirelists because they consist of a list of components and interconnections. VHDL netlists are often generated automatically from a schematic or as part of the output of a synthesis tool.

Gate-level simulation is often performed during the latter stages of the design process after the design has been synthesized from a higher level description. Such synthesized designs can contain hundreds of thousands of gates so simulation performance is an important issue.

Circuit Level

The circuit level consists of interconnected active and passive components. Circuit behavior within time domain is represented by means of nonlinear differential equations. This level acts as a link to physical representations of digital circuits.

Mixed-Signal Systems

Mixed-signal systems and circuits generate and consume both continuous and discrete signals in the digital partition, while in the analog partition the values are continuous. Digital operates in the discrete time domain while analog operates with continuous time values so signal values must be converted as they move from one domain to the other. Each partition can be denoted at any abstraction level.

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Cadence VHDL-AMS OverviewProduct Version 22.09, April 2022

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VHDL-AMS Modeling Styles