Virtuoso Layout Suite EXL Features and Flows

The features and flows available in Layout EXL are summarized below, along with instructions on how to enable each feature in the Layout EXL window and a link to more detailed information.

• Electrically Aware Design
  The electrically aware design (EAD) flow lets you capture the current data from design simulations, extract and visualize RC parasitics as you edit the layout, perform EM checks, and fix violations. You can further extract parasitics from a partial or complete layout and rerun simulations to check if the output specifications are met.
  You can access the electrically aware design functionality both from the EAD menu (which is automatically installed when you launch Layout EXL) and in the EAD workspace, available from the drop-down list in the toolbar.
• Simulation Driven Routing
  The simulation driven routing (SDR) capability elevates Virtuoso from an electrically aware design environment to a simulation driven design environment. It addresses many of the electromigration and parasitic challenges of critical circuits and advanced-node designs, offering the layout designer an innovative and predictable flow to help meet current density constraints, significantly reduce sign-off times, and improve productivity and design reliability.
  You can access the simulation driven routing functionality from the SDR Toolbar, which is installed automatically when you launch Layout EXL.
• Virtuoso Concurrent Layout Editing
  Virtuoso Concurrent Layout is a layout editing environment that lets multiple designers work concurrently on different parts of the same top cellview within Virtuoso. This increases the overall productivity of the layout design team by allowing them to work on different aspects of a single design in parallel.
  To access the feature, choose the Concurrent_Layout workspace from the drop-down list in the toolbar.
• Design Planning and Analysis
  The advanced design planning and analysis feature provides hierarchical generation capabilities supported in an innovative layout-place-route solution for both advanced and mature node designs. The design planning and analysis feature supports informed planning decisions earlier in the design cycle, which are based on real-time congestion analysis data provided by the fully integrated Congestion Analysis assistant.
  To access the feature, choose the Design_Planning workspace from the drop-down list in the toolbar.
• Congestion Analysis
  The Congestion Analysis assistant facilitates the quick and accurate modeling of routing congestion to help improve floorplanning, optimize pin generation and placement, and reduce overall die size. The feature lets you extract, display, and analyze routing congestion both visually and statistically, and offers sophisticated tools facilitating the targeted optimization of routing paths for critical nets and net groups.
  To open the assistant, choose the Congestion_Analysis workspace from the drop-down list in the toolbar.
• Virtuoso Automated Device Placement and Routing Flow
  The Virtuoso automated device placement and routing flow comprises a series of tasks to generate automatically placed and routed layouts. The flow enables you to quickly generate placed and routed layouts that are constraint compliant and LVS correct, and follow DRCs as captured in the Virtuoso technology file. The layouts also incorporate base layer fill, as typically required in advanced nodes. These layouts can be used to extract parasitics for re-simulation to identify issues early on, without waiting for the final sign-off, and can be easily modified and updated to generate the final layout for sign-off.
  To access the functionality, open the Auto P&R assistant that is automatically available in the Layout EXL environment.

The following features have feature-licensing requirements in addition to requiring Layout EXL platform and the Virtuoso_Layout_Suite_EXL license as a base. Check the feature documentation for more details.

• Virtuoso RF Solution
  The Virtuoso RF solution allows ICs to be imported from different technologies and into a single package design, enabling package designers to assemble and simulate the package on a single platform.
  To access the RF solution, set the Virtuoso_RF_Option shell environment variable before you launch Virtuoso. You cannot open a package layout in Layout EXL unless this environment variable is set.
• Virtuoso Photonics Solution
  The Virtuoso Photonics solution supports an Electronic-Photonic Design Environment (EPDA) framework that allows integration and implementation of electrical and optical signals using a single design framework.
  If you already have access to the Virtuoso Studio design environment, you can invoke the additional Photonics capabilities supported in Virtuoso by using the Virtuoso_Photonics Option (VPO) license. The VPO license can be accessed by setting the shell environment variables:
  setenv Virtuoso_Photonics_Option t
  If you do not already have a dedicated license to access the Virtuoso Studio design environment, you can check out the Virtuoso_Photonics_Platform (VPP) license by setting the shell environment variable:
  setenv Virtuoso_Photonics_Platform t

Related Topics

Virtuoso Layout Viewer

Virtuoso Electrically Aware Design Flow

Virtuoso Simulation Driven Interactive Routing Flow

Getting Started with Virtuoso Concurrent Layout

Virtuoso Design Planning and Analysis

Running Congestion Analysis

Virtuoso RF Solution

Virtuoso Photonics Solution

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