---

Contents

---

1

Introduction to Virtuoso RF Solution

License Requirements of Virtuoso RF Solution

Schematic/Layout Views in the Virtuoso RF Solution/Virtuoso MultiTech Environment

2

Flows in Virtuoso RF Solution

Virtuoso RFIC EMX Quantus Flow

Virtuoso RF Schematic-Driven Flow

Virtuoso RF Library Import Flow

Virtuoso RF ECO Flow

Virtuoso Integrity 3D-IC Flow

Virtuoso Stacked Silicon Solution Flow

Virtuoso Schematic Editor Driven SiP Layout Flow

Virtuoso Schematic Editor Driven Layout MXL Flow

SiP Layout Option to Virtuoso Schematic Editor Flow

SiP to Virtuoso Layout Assisted Import and Export Flows

Multi-Technology Enablement Flow

3

Introduction to Packaging

Packaging-Related Terminology

Package Definition

Components of a Package

Bumps (IO pads)

Through Silicon Vias (TSVs)

Silicon Interposers

Padstacks

Stackup Information in Substrate

Wafer-Level Packaging

Phases of Package Creation

Template Files

Constraint Definition

Placement

Thermal Analysis

Die-to-Component I/O Net Assignment

Routing Concerns

Voiding and Connectivity

4

Import Libraries and ICs

Technology File

Die Export

Die Audit Overview

5

Package Schematic Creation

6

Package Layout Creation

Generate from Source

7

Edit-in-Concert

8

Stacked Modules Management

Die Operations

9

Verify the Package

10

3D Electromagnetic Simulation

Types of EM Solvers in Virtuoso RF Solution

Extracted Views Creation

Extracted View Creation From the Schematic

Extracted View Creation From Smart View

Extracted Views Creation From Full Cellviews

11

Interoperability with SiP

Return to top