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Virtuoso Power Manager Flow
The flows in Virtuoso Power Manager offer an automated solution for capturing the power intent of a design. Usually for small designs, it is convenient to write the power intent manually. As the design complexity increases, it becomes mandatory to have an automated solution. The complexity in designs can be about multiple power domains, different voltage levels, switchable power domains, or the functionality implemented using low power design techniques by the use of low power special cells, such as level shifters, isolation cells, and power switches.
You can seamlessly capture the power intent of digital, analog, and mixed-signal designs and verify that the power intent has been implemented correctly. In addition, you can also track power intent changes during IP authoring. You can export the power intent of the IP design in the standard IEEE 1801 format, which can be further utilized by the SOC verification team for full-chip low power verification.
Related Topics
Recommended Use Model for Power Intent Creation and Verification
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