Recommended Use Model for Power Intent Creation and Verification

Follow the use model described by the steps given below to get an accurate power intent for your design:

1. Prepare a setup file for importing power intent on a design, running In-Design Checks, or extracting power intent from a design. This requires registration of the components that describe power intent. For example, you can register power nets, ground nets, and special low power cells.
   See Setup for Automatic Extraction of Power Intent.
2. Register special low power cells or custom standard cells by using the Liberty definitions or a 1801 special cell definition file.
   See Registration of Low Power Special Cells and Standard Cells.
3. If there is an incomplete hierarchical design that already has the power intent available, for example, a digital block, use the import 1801 flow to complete the power connectivity of that hierarchical design. Perform the schematic hierarchy check while importing an existing 1801 power specification on a hierarchical schematic.
   See Power Intent Import.
4. Open the design in Power Manager and check for an existence of primitive cell instances or single supply cells, such as transistors or resistors at the top level of designs. If these cells exist at the top level, create one or more new blocks and move these cells to the new blocks.
   This is required because the primitive instances do not have a power pin or ground pin and therefore, are not assigned to any power domain or domain mapping. In such a case, the design netlist generated for the verification includes these primitive cell instances, but the exported 1801 file does not include these instances. As a result, during power intent verification, when CLP does not find the power intent for these instances in the1801 file, it reports errors or warnings. These can be avoided during netlisting by using the appropriate flags to customize the netlist so that it does not extract primitives.
   See Verifying Power Intent of a Design.
5. Load the setup file, including the customizations required for running the In-Design checks. Check the analog or mixed signal custom blocks using static, pre-configured in-design checks, and verify the low power design implementation.
   See Running In-Design Checks.
   Once the results obtained are satisfactory, extract the power intent details of the top design. Power Manager extracts the power intent of hierarchical design, which can be exported to a 1801 file. A separate OA view called the power view is also generated at the time of extraction that captures all the setup information, internal data structure, and the power intent details. This view can be reused in the same Virtuoso session.
   See Exporting Power Intent of a Design.
6. The standard and special cells in the design should have their associated schematic or Verilog Symbol views with the PG pin information. This is a requirement for the tool to generate a Verilog netlist with the PG information, before verifying the power intent.
   
   CLP is a digital verification tool. It supports the inherited connections and global nets with explicit p/g connections to the standard cells because it needs maximum low power check coverage. CLP performs physical low power verification by tracing the explicit p/g nets and deriving power domain information accordingly. This is the most comprehensive design structural check.
7. Verify the power intent of your design.
   See Verifying Power Intent of a Design.

Related Topics

Virtuoso Power Manager Flow

Basic Flow in Power Manager