Die-to-Component I/O Net Assignment
At this phase of component design, the only logic in the design database is the die and, in the case of FCMs, the die-to-die interconnect. This provides for efficient component design because die-to-component logic can be optimized only after you have defined the component description and placement. Without either piece, component I/O assignment becomes a blind exercise that results in poor interconnect efficiency.
With only die logic defined, you can optimize I/O assignment for routing and performance with minimization of interconnect length and logic criss-crossing.
Priority Nets
Prior to signal pin assignment, you should identify critical signals as priority connections. Depending on performance requirements, these signals may need to be the “shortest possible distance” to the component I/O, in which case manual pin assignment may be required. Many ECAD systems allow you to attach a special attribute to a net that requires a priority connection.
Pin Assignment
The first step in optimizing pin assignment is to determine which component I/Os feed power and ground connections. Most companies preassign pins in a netlist. The power/ground pin assignment determines the remaining available component pins that can be used for signal assignment. Of course, there must be enough I/O pins remaining to accommodate the number of signal I/Os.
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